公开(公告)号：KR1020090119461A

公开(公告)日：2009-11-19

申请号：KR1020080045521

申请日：2008-05-16

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 차대길 ,  신중훈 ,  박윤동 ,  진영구 ,  양문승 ,  조인성 ,  장지수

IPC: G02B6/13 ,  B82Y30/00

CPC classification number: H01S3/0632 ,  H01S3/0637 ,  H01S3/0933 ,  H01S3/09403 ,  H01S3/1608 ,  H01S3/1691

Abstract: PURPOSE: An optical amplifying medium, a manufacturing method thereof, and an optical device including the optical amplifying medium are provided to used as an optical inter connector between chips by being easily applied to an existing semiconductor device. CONSTITUTION: A first material layer and a second material layer are formed on a substrate(100). The first material layer(10) dopes an activator. The second material layer(20) includes a sensitizer. The activator is erbium. The sensitizer is silicon nano cluster. The substrate is annealed in order to form the sensitizer inside the second material layer.

Abstract translation: 目的：提供一种光放大介质及其制造方法以及包括该光放大介质的光学器件，以容易地应用于现有的半导体器件，作为芯片间的光学连接器。 构成：在基板（100）上形成第一材料层和第二材料层。 第一材料层（10）涂覆活化剂。 第二材料层（20）包括敏化剂。 活化剂是铒。 敏化剂是硅纳米簇。 为了在第二材料层内部形成敏化剂，将基板退火。

公开(公告)号：KR1020090109804A

公开(公告)日：2009-10-21

申请号：KR1020080035217

申请日：2008-04-16

Applicant: 삼성전자주식회사

Inventor： 김석필 ,  박윤동 ,  구준모

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/249 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L27/2463

Abstract: PURPOSE: A non-volatile memory device and method of fabricating the same are provided to increase the number of first electrodes and second electrodes for high integration. CONSTITUTION: The non-volatile memory device includes at least one data storage layer(130), at least one first electrode(110), at least one second electrode(140). The second electrode is arranged to cross the first electrode. The data storage layer is interposed in the crossing potion of the second electrode with the first electrode. At least first electrode includes a junction diode(D) connected to the data storage layer.

Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以增加用于高集成度的第一电极和第二电极的数量。 构成：非易失性存储器件包括至少一个数据存储层（130），至少一个第一电极（110），至少一个第二电极（140）。 第二电极布置成与第一电极交叉。 数据存储层插入第二电极的交叉部分与第一电极。 至少第一电极包括连接到数据存储层的结二极管（D）。

公开(公告)号：KR1020090090063A

公开(公告)日：2009-08-25

申请号：KR1020080015310

申请日：2008-02-20

Applicant: 삼성전자주식회사

Inventor： 조경래 ,  김재홍 ,  박윤동 ,  공준진 ,  채동혁

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

Abstract: A memory device and a memory reading method thereof are provided to improve the performance of an error correction by performing the ECC(Error Correction Code) decoding of the data read from the multi bit cells. A memory device(100) includes a multi bit cell array(110), an error detector(120), and a data estimator(130). The error detector reads a first data page from a memory page(111) inside the multi bit cell array. The error detector performs ECC decoding of the first data page and detects the error bit of the first data page. The estimator identifies the multi bit cell with an error bit. The estimator estimates the data of the second data page stored in the identified multi bit cell.

Abstract translation: 提供了一种存储器件及其存储器读取方法，以通过执行从多位单元读取的数据的ECC（纠错码）解码来改善纠错的性能。 存储器件（100）包括多位单元阵列（110），误差检测器（120）和数据估计器（130）。 误差检测器从多位单元阵列内部的存储器页（111）读取第一数据页。 误差检测器执行第一数据页的ECC解码并检测第一数据页的错误位。 估计器使用错误位来识别多位单元。 估计器估计存储在所识别的多位单元中的第二数据页的数据。

公开(公告)号：KR1020090079694A

公开(公告)日：2009-07-22

申请号：KR1020080005852

申请日：2008-01-18

Applicant: 삼성전자주식회사

Inventor： 진영구 ,  박윤동 ,  김원주 ,  김석필 ,  이승훈

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  B82Y10/00

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to reduce a manufacturing cost by using a stacked structure for simplifying a manufacturing process. A non-volatile memory device(100c) includes at least one or more semiconductor pillar(145a), at least one or more first control gate electrode(110a), at least one or more second control gate electrode(110b), a first charge storage layer, and a second charge storage layer. The first control gate electrode is arranged in one side of the semiconductor pillar. The second control gate electrode is arranged in the other side of the semiconductor pillar. The first charge storage layer is inserted into a space between the first control gate electrode and the semiconductor pillar. The second charge storage layer is inserted between the second control gate electrode and the semiconductor pillar.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过使用用于简化制造工艺的堆叠结构来降低制造成本。 非易失性存储器件（100c）包括至少一个或多个半导体柱（145a），至少一个或多个第一控制栅电极（110a），至少一个或多个第二控制栅电极（110b），第一电荷 存储层和第二电荷存储层。 第一控制栅极布置在半导体柱的一侧。 第二控制栅极布置在半导体柱的另一侧。 第一电荷存储层被插入到第一控制栅电极和半导体柱之间的空间中。 第二电荷存储层插入在第二控制栅电极和半导体柱之间。

公开(公告)号：KR1020090027004A

公开(公告)日：2009-03-16

申请号：KR1020070092149

申请日：2007-09-11

Applicant: 삼성전자주식회사

Inventor： 김석필 ,  진영구 ,  박윤동

IPC: H01L27/108

CPC classification number: H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: A capacitorless DRAM and its operation method are provided to isolate the charge storage layer from the source area and drain region and to improve data retention property. The semiconductor layer(310) is separated from the upper side of the substrate(300). The semiconductor layer comprises the source region(S1), and the drain region(D1) and channel region(C1). The charge storage layer(H1) is equipped on the channel region. The gate(400) is formed in the top of the substrate. The gate contacts with the channel region and charge storage layer. The channel region is protruded than the source region and drain region. The charge storage layer is separated from the source region and drain region.

Abstract translation: 提供无电容DRAM及其操作方法，以将电荷存储层与源极区和漏极区隔离，并提高数据保留性能。 半导体层（310）从衬底（300）的上侧分离。 半导体层包括源极区（S1）和漏极区（D1）以及沟道区（C1）。 电荷存储层（H1）配置在通道区域上。 栅极（400）形成在衬底的顶部。 栅极与沟道区和电荷存储层接触。 沟道区域比源区域和漏极区域突出。 电荷存储层与源极区和漏极区分离。

公开(公告)号：KR1020080112876A

公开(公告)日：2008-12-26

申请号：KR1020070061874

申请日：2007-06-22

Applicant: 삼성전자주식회사

Inventor： 박주희 ,  현재웅 ,  조경래 ,  박윤동 ,  이승훈 ,  권기원

IPC: G11C16/26 ,  G11C16/28 ,  G11C16/10

CPC classification number: G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A non-volatile memory device and operation method thereof is provided to improve a speed of a read operation by being no need to performing a read operation about all bits of memory cells. A non-volatile memory device comprises a plurality of memory cells(MC1~MCn), a memory block(MB11~MB4n), and a controller. The memory cells stores a respective date. The memory block respectively includes a block state confirmation cell storing information about the number of bit filled in the memory cell. The controller reads a data from the memory block to a bit stored in the block state confirmation cell.

Abstract translation: 提供了一种非易失性存储器件及其操作方法，用于通过不需要执行关于存储器单元的所有位的读取操作来提高读取操作的速度。 非易失性存储器件包括多个存储器单元（MC1〜MCn），存储块（MB11〜MB4n）和控制器。 存储单元存储相应的日期。 存储块分别包括存储关于在存储单元中填充的位的数量的信息的块状态确认单元。 控制器从存储器块读取数据到存储在块状态确认单元中的位。

公开(公告)号：KR1020080100671A

公开(公告)日：2008-11-19

申请号：KR1020070046662

申请日：2007-05-14

Applicant: 삼성전자주식회사

Inventor： 박주희 ,  현재웅 ,  박윤동 ,  조경래 ,  변성재 ,  송승환 ,  공준진 ,  박성정

IPC: G11C16/10

CPC classification number: H01L29/7883 ,  G11C16/10

Abstract: A memory cell programming method is provided to improve programming speed by programming a plurality of memory block groups. In a memory cell programming method of programming M bit data in a plurality of memory blocks, a plurality of memory blocks is divided into a plurality of memory block groups. In a plurality of memory blocks, An i(i is the natural number less than M) number of bit is written in a plurality of memory block groups having memory block groups more than 2, and i+1 number of the bit in the memory block group more than 2.

Abstract translation: 提供存储器单元编程方法以通过编程多个存储器块组来提高编程速度。 在多个存储块中对M位数据进行编程的存储单元编程方法中，多个存储块被分成多个存储块组。 在多个存储块中，将具有大于2的存储块组的多个存储块组写入比特的An i（i是小于M的自然数）的比特，并且存储器中的i + 1比特数 块组超过2。

公开(公告)号：KR1020080069865A

公开(公告)日：2008-07-29

申请号：KR1020070007641

申请日：2007-01-24

Applicant: 삼성전자주식회사

Inventor： 김원주 ,  박윤동 ,  구준모 ,  김석필 ,  이태희

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/7881 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L21/28273

Abstract: A nonvolatile memory device and a method for operating the same are provided to block current flow from a unit cell to bit lines by turning off an assistant transistor so as to solve a problem that the off-cell is not read. A pair of control gate electrodes(135) are provided on a semiconductor substrate(105). A source region(140) is placed between the control gate electrodes. A pair of assistant gate electrodes(115) are recessed in the semiconductor substrate. A pair of drain regions(145) are limited to the semiconductor substrate respectively. The semiconductor substrate has a bulk wafer structure, and an epitaxial layer is formed on the bulk wafer. A pair of tunneling insulating layers(120) are placed between the semiconductor substrate and charge storage layers. A pair of blocking insulating layers(130) are placed between the control gate electrodes and the charge storage layers. A pair of gate insulating layers(110) are placed between the assistant gate electrodes and the semiconductor substrate. First and second channel regions(165,170) are connected directly by placing the control gate electrodes and the assistant gate electrodes horizontally. The drain regions are connected with bit lines(160).

Abstract translation: 提供一种非易失性存储器件及其操作方法，通过关闭辅助晶体管来阻止从单元电池到位线的电流，从而解决了不读取电池的问题。 一对控制栅电极（135）设置在半导体衬底（105）上。 源极区域（140）被放置在控制栅电极之间。 一对辅助栅极电极（115）凹入半导体衬底。 一对漏极区域（145）分别限于半导体衬底。 半导体衬底具有体晶片结构，并且在体晶片上形成外延层。 一对隧道绝缘层（120）被放置在半导体衬底和电荷存储层之间。 在控制栅电极和电荷存储层之间放置一对阻挡绝缘层（130）。 一对栅极绝缘层（110）被放置在辅助栅电极和半导体衬底之间。 第一和第二通道区域（165,170）通过水平放置控制栅电极和辅助栅电极而直接连接。 漏极区域与位线（160）连接。

公开(公告)号：KR1020070092502A

公开(公告)日：2007-09-13

申请号：KR1020060022728

申请日：2006-03-10

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  박윤동 ,  황현상 ,  이동수

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/12 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/56 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A resistive memory device is provided to decrease the consumption of power by reducing remarkably on-current compared to a conventional resistive memory device using a doped oxide layer formed on an RRAM(Resistance Random Access Memory) material. A resistive memory device includes a lower electrode(21), a first oxide layer, a current control layer and an upper electrode. The first oxide layer(22) is formed on the lower electrode. The first oxide layer is capable of storing information by using two resistive states. The current control layer(23) is formed on the first oxide layer. The current control layer is made of a second oxide material. The upper electrode(24) is formed on the current control layer. The first oxide layer is made of one selected from a group consisting of NiOx, ZrOx, Nb2O5-x, HfO, ZnO, WC3, CoO, CuO2, and TiO2. The current control layer is made of one selected from a group consisting of a transitional metal doped ZnOx and RuOx.

Abstract translation: 与使用在RRAM（电阻随机存取存储器）材料上形成的掺杂氧化物层的常规电阻式存储器件相比，提供了一种电阻性存储器件来减少功率消耗。 电阻式存储器件包括下电极（21），第一氧化物层，电流控制层和上电极。 第一氧化物层（22）形成在下电极上。 第一氧化物层能够通过使用两个电阻状态来存储信息。 电流控制层（23）形成在第一氧化物层上。 电流控制层由第二氧化物材料制成。 上电极（24）形成在电流控制层上。 第一氧化物层由选自NiO x，ZrO x，Nb 2 O 5-x，HfO，ZnO，WC 3，CoO，CuO 2和TiO 2中的一种构成。 电流控制层由选自过渡金属掺杂的ZnOx和RuOx组成的组中的一个制成。

公开(公告)号：KR100718149B1

公开(公告)日：2007-05-14

申请号：KR1020060011829

申请日：2006-02-07

Applicant: 삼성전자주식회사

Inventor： 박윤동 ,  김석필

IPC: H01L29/78