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公开(公告)号：KR1020060128567A
公开(公告)日：2006-12-14
申请号：KR1020050050108
申请日：2005-06-11
Applicant: 재단법인서울대학교산학협력재단 , 삼성전자주식회사
IPC: H01L27/115
CPC classification number: G11C16/0483 , H01L27/115 , G11C16/0408
Abstract: A NAND-type flash memory array and an operating method thereof are provided to reduce program disturbance by using a body biasing contact region connected to an active region on a lower portion of a side of a second select gate line. At least one bit line(B/L0,B/L1) is formed on an SOI substrate. A first select transistor, plural memory cells, and a second select transistor are serially connected to each bit line by their geared sources and drains. The source of the second select transistor is electrically connected to a common source line(CSL) vertically arranged to the bit line. A gate of the first select transistor and a gate of the second select transistor are respectively connected to a first select gate line(SSL) and a second select gate line(GSL) arranged to be crossed with the bit line. Gates of the memory cells are respectively connected to plural word lines(W/L0,W/L1) arranged to be crossed with the bit line. A body biasing contact region(BBC) is connected to an active region on a lower portion of a side of the second select gate line.
Abstract translation: 提供NAND型闪速存储器阵列及其操作方法以通过使用与第二选择栅极线的一侧的下部的有源区连接的主体偏置接触区域来减少编程干扰。 在SOI衬底上形成至少一个位线（B / L0，B / L1）。 第一选择晶体管，多个存储单元和第二选择晶体管通过其齿轮源和排水管串联连接到每个位线。 第二选择晶体管的源极电连接到垂直地布置到位线的公共源极线（CSL）。 第一选择晶体管的栅极和第二选择晶体管的栅极分别连接到布置成与位线交叉的第一选择栅极线（SSL）和第二选择栅极线（GSL）。 存储单元的门分别连接到布置成与位线交叉的多个字线（W / L0，W / L1）。 主体偏置接触区域（BBC）连接到第二选择栅线的一侧的下部的有源区域。
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公开(公告)号：KR100603721B1
公开(公告)日：2006-07-24
申请号：KR1020050050107
申请日：2005-06-11
Applicant: 재단법인서울대학교산학협력재단 , 삼성전자주식회사
IPC: H01L21/336
Abstract: 본 발명은 SOI 기판 상에 직렬 연결된 소자의 바디 바이어싱 구조에 관한 것으로, 공통 소스/드레인 영역의 정션 깊이를 얕게 만듦으로써, 통상적인 벌크 MOSFET처럼 하나의 바디 바이어싱 콘택만으로도 여러 개의 소자에 대해 바디 바이어싱을 가능하게 하여 SOI 기판의 플로팅 바디 효과(floating body effect)를 제거하는 효과가 있다.
SOI, 바디, 바이어스, 플로팅Abstract translation: 本发明涉及在SOI衬底上串联连接的元件的体偏置结构，并且通过使公共源极/漏极区域的结深度浅，可以提供一种体 从而实现偏置并消除SOI衬底的浮体效应。
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公开(公告)号：KR102248835B1
公开(公告)日：2021-05-10
申请号：KR1020140130236
申请日：2014-09-29
Applicant: 삼성전자주식회사
Abstract: 본발명에따른제 1 및제 2 비트라인에각각연결되는제 1 및제 2 페이지버퍼를포함하는불 휘발성메모리장치의동작방법은: 상기제 1 페이지버퍼의제 1 래치에저장된데이터에따라상기제 1 페이지버퍼의제 1 및제 2 래치노드를제 1 레벨로바이어스하는단계; 상기제 1 래치노드와인접한, 상기제 2 페이지버퍼의센싱노드를프리차지하는단계; 그리고상기센싱노드를프리차지하는동안상기제 1 래치에저장된데이터를상기제 1 페이지버퍼의제 2 래치로덤핑하는단계를포함하되, 상기센싱노드의프리차지동작이완료된후에도, 상기제 1 래치노드는상기제 1 레벨로유지되도록제어된다.
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公开(公告)号：KR102235492B1
公开(公告)日：2021-04-05
申请号：KR1020140110864
申请日：2014-08-25
Applicant: 삼성전자주식회사
Abstract: 본발명의실시예에따른복수의메모리셀들을프로그램하는불휘발성메모리장치의프로그램검증방법은복수의검증전압들을인가하는단계; 및상기복수의검증전압들중 하나의검증전압을기반으로상기복수의메모리셀들중 서로다른목표문턱전압산포범위들을각각갖는메모리셀들의프로그램완료여부를판별하는단계를포함한다.
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Patent Agency Ranking
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公开(公告)号：KR1020140065185A
公开(公告)日：2014-05-29
申请号：KR1020120132420
申请日：2012-11-21
Applicant: 삼성전자주식회사
CPC classification number: G11C16/08 , G11C7/04 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26
Abstract: The present invention relates to a semiconductor memory device which applies a temperature-compensated word line voltage to a word line in a data reading operation. In the present invention, disclosed is the semiconductor memory device comprising a memory cell array which includes a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells which are connected to the word lines and the bit lines; and a word line voltage applying unit which applies a temperature-compensated read voltage to a selected word line and applies a temperature-compensated pass voltage to an unselected word line in the reading operation.
Abstract translation: 半导体存储器技术领域本发明涉及在数据读取操作中将温度补偿字线电压施加到字线的半导体存储器件。 在本发明中，公开了包括存储单元阵列的半导体存储器件，该存储单元阵列包括连接到字线和位线的多个字线，多个位线和多个非易失性存储器单元; 以及字线电压施加单元，其对所选择的字线施加温度补偿读取电压，并且在读取操作中将温度补偿通过电压施加到未选择的字线。
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公开(公告)号：KR1020140055738A
公开(公告)日：2014-05-09
申请号：KR1020120122985
申请日：2012-11-01
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/3436 , G11C16/344
Abstract: A non-volatile memory device according to an embodiment of the present invention comprises: a memory cell array including word lines and bit lines; and a control logic which performs a program operation to program memory cells connected to a selected word line by applying a program voltage to the selected word line of the memory cell array, and performs a delete operation to delete the memory cells by applying a delete voltage and a delete verify voltage to the selected word line, wherein the control logic extracts information of the deleted state of the memory cell by applying a read voltage to the selected word line, and controls the level of the delete verify voltage based on the delete state information.
Abstract translation: 根据本发明实施例的非易失性存储器件包括：包括字线和位线的存储单元阵列; 以及控制逻辑，其通过对存储单元阵列的所选择的字线施加编程电压来执行编程连接到所选字线的存储器单元的编程操作，并且通过施加删除电压来执行删除操作以删除存储器单元 以及对所选择的字线的删除验证电压，其中，所述控制逻辑通过对所选择的字线施加读取电压来提取所述存储器单元的删除状态的信息，并且基于所述删除状态来控制所述删除验证电压的电平 信息。
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公开(公告)号：KR1020130142421A
公开(公告)日：2013-12-30
申请号：KR1020120065626
申请日：2012-06-19
Applicant: 삼성전자주식회사
IPC: G11C16/06
CPC classification number: G11C16/3418 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a nonvolatile memory chip which includes a static latch and a dynamic latch which receives data from the static latch through a floating node, a device controller which controls the operation of the nonvolatile memory chip, and a refresh controller which controls the refresh operation of the dynamic latch. The dynamic latch includes a storage node, a writing transistor which writes the data of the floating node on the storage node and a reading transistor which reads the data of the storage node. The writing transistor and the reading transistor share the floating node.
Abstract translation: 提供非易失性存储器件。 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器和通过浮动节点从静态锁存器接收数据的动态锁存器，控制非易失性存储器芯片的操作的器件控制器和控制非易失性存储器芯片的刷新控制器 动态锁存器的刷新操作。 动态锁存器包括存储节点，将浮动节点的数据写入存储节点的写入晶体管和读取存储节点的数据的读取晶体管。 写入晶体管和读取晶体管共享浮动节点。
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