公开(公告)号：KR1020100093354A

公开(公告)日：2010-08-25

申请号：KR1020090012502

申请日：2009-02-16

Applicant: 삼성전자주식회사

Inventor： 심현준 ,  김완돈 ,  최석헌 ,  이한신 ,  백인규 ,  자오진시 ,  임은경

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/04 ,  G11C13/0004 ,  H01L29/513 ,  H01L29/517 ,  H01L45/1233

Abstract: PURPOSE: A method for manufacturing a resistance memory device is provided to form a resistance oxide layer which is physically and chemically stabilized without an etching process by forming the resistance oxide layer through the diffusion of oxygen to the upper surface of the first electrode through a second electrode. CONSTITUTION: A first electrode(12) is formed inside a lower insulation layer(10). A second electrode(14) is formed on a first electrode. The second electrode is formed on the deposition process using an organic metal precursor. The upper surface of the first electrode connected to the second electrode is converted into a resistance oxidation layer(16) by diffusing the oxygen to the upper surface of the first electrode through the second electrode.

Abstract translation: 目的：提供一种用于制造电阻存​​储器件的方法，以形成物理和化学稳定的电阻氧化层，无需蚀刻工艺，通过通过第二电极通过氧气扩散到第一电极的上表面形成电阻氧化物层 电极。 构成：第一电极（12）形成在下绝缘层（10）的内部。 在第一电极上形成第二电极（14）。 使用有机金属前体在沉积工艺上形成第二电极。 通过第二电极将氧扩散到第一电极的上表面，将连接到第二电极的第一电极的上表面转换成电阻氧化层（16）。

公开(公告)号：KR1020100007200A

公开(公告)日：2010-01-22

申请号：KR1020080067718

申请日：2008-07-11

Applicant: 삼성전자주식회사

Inventor： 조금석 ,  이한신 ,  백인규 ,  심현준 ,  임은경

IPC: H01L21/28 ,  B82B1/00 ,  B82Y40/00

CPC classification number: H01L21/76838 ,  B82Y40/00 ,  H01L21/32139 ,  H01L21/76837

Abstract: PURPOSE: A method for forming a semiconductor device is provided to implement high integration by reducing the width of components with a nano scale. CONSTITUTION: A nano structure is formed from a catalyst pattern. The nanostructure is grown on the catalyst pattern. An insulation layer(21) is formed on a substrate(10). The insulation layer surrounds the nano structure. The top of the nano structure is exposed by the planarization of the insulation layer. The opening is formed by removing the nano structure and the catalyst pattern. The opening is defined by the insulation layer. A variable resistance pattern(27) is formed in the opening.

Abstract translation: 目的：提供一种用于形成半导体器件的方法，通过减小纳米级元件的宽度来实现高集成度。 构成：由催化剂图案形成纳米结构。 纳米结构在催化剂图案上生长。 绝缘层（21）形成在基板（10）上。 绝缘层围绕纳米结构。 纳米结构的顶部通过绝缘层的平坦化暴露。 通过除去纳米结构和催化剂图案形成开口。 开口由绝缘层限定。 在开口中形成可变电阻图案（27）。

公开(公告)号：KR1020090026580A

公开(公告)日：2009-03-13

申请号：KR1020070091660

申请日：2007-09-10

Applicant: 삼성전자주식회사

Inventor： 이장은 ,  김대겸 ,  정준호 ,  오세충 ,  남경태 ,  심현준

IPC: H01L27/105

CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: A resistance memory device and a method of formation thereof are provided to increase the reliability of the resistance memory device by forming a bottom electrode, variable resistance oxide film, and a middle electrode within a contact hole. A resistance memory device comprises a semiconductor substrate(100) including a conductive pattern(105); an insulating layer(110) having the contact hole of the semiconductor substrate; a bottom electrode(120) contacting with the conductive pattern within the contact hole; a middle electrode(140) arranged on the bottom electrode within the contact hole; a variable resistance oxide film(130) interposed between the bottom electrode and the middle electrode; a buffer oxide layer(150) formed on the insulating layer and the middle electrode; an upper electrode(160) formed on the buffer oxide layer.

Abstract translation: 提供电阻记忆装置及其形成方法，以通过在接触孔内形成底部电极，可变电阻氧化物膜和中间电极来增加电阻存储装置的可靠性。 电阻存储器件包括包括导电图案（105）的半导体衬底（100）; 绝缘层（110），具有半导体衬底的接触孔; 底部电极（120），其与所述接触孔内的所述导电图案接触; 布置在接触孔内的底部电极上的中间电极（140） 介于底部电极和中间电极之间的可变电阻氧化膜（130）; 形成在绝缘层和中间电极上的缓冲氧化物层（150）; 形成在缓冲氧化物层上的上电极（160）。