公开(公告)号：KR1019990030830A

公开(公告)日：1999-05-06

申请号：KR1019970051264

申请日：1997-10-06

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  서태욱

IPC: H01L21/76

Abstract: 반도체 장치의 제조 방법에 관해 개시한다. 본 발명에 따르면, 질화막 스페이서를 형성하기 전에 반도체 기판의 배면에 부수적으로 형성된 질화막을 제거하여 반도체 기판이 받는 응력을 최소화한다. 반도체 기판의 배면에 형성된 질화막의 제거시 기판 전면에 형성된 질화막의 손상을 최소화하기 위하여 기판 전면에 형성된 질화막위에 보호막을 형성한다. 그리고 반도체 기판의 배면에 형성된 질화막의 제거는 상기 반도체 기판의 배면에 형성된 질화막만을 선택적으로 제거하는 용액을 사용하여 실시하고, 배면에 형성되어 있는 질화막 제거후 보호막을 제거할 때에는 보호막만을 선택적으로 제거하는 용액을 사용하여 실시한다.

公开(公告)号：KR100675280B1

公开(公告)日：2007-01-29

申请号：KR1020050054167

申请日：2005-06-22

Applicant: 삼성전자주식회사

Inventor： 이효종 ,  이선정 ,  서봉석 ,  신홍재 ,  이내인 ,  이경우 ,  정세영 ,  안정훈 ,  이수근

IPC: H01L21/28

CPC classification number: H01L23/53238 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체소자의 선택적 구리 합금 배선을 제공한다. 상기 배선은 기판, 상기 기판 상에 배치된 절연막, 및 상기 절연막 내에 배치된 제 1 배선을 포함한다. 상기 제 1 배선은 제 1 순수 구리 패턴을 구비한다. 또한, 상기 절연막 내에 상기 제 1 배선보다 큰 폭을 가지는 제 2 배선이 제공된다. 상기 제 2 배선은 구리 합금 패턴을 구비한다. 상기 구리 합금 패턴은 구리(Cu) 및 첨가물질로 이루어진 합금 층일 수 있다. 상기 선택적 구리 합금 배선의 형성방법 또한 제공된다.

公开(公告)号：KR1020050015190A

公开(公告)日：2005-02-21

申请号：KR1020030053890

申请日：2003-08-04

Applicant: 삼성전자주식회사

Inventor： 안정훈 ,  이효종 ,  이경태 ,  이경우 ,  이수근 ,  서봉석

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: PURPOSE: A metallic interconnection structure for preventing voids and a method for interconnecting metals are provided to improve device stability by forming a void diffusion barrier layer on a diffusion path of the voids into a via contact hole. CONSTITUTION: A lower metallic interconnection pattern is implemented in a first interlayer dielectric(106). A metallic insulating layer(112) includes a via contact hole(120a,120b) exposing a portion of a surface of the lower metallic interconnection pattern. A second interlayer dielectric includes a trench for exposing the via contact hole on the metallic insulating layer. A barrier metallic layer(122a,122b) is formed on a side portion of the via contact hole and the exposed surface of the second lower metallic interconnection pattern. A first upper metallic interconnection pattern(124a) fills the via contact hole and a portion of the trench. A void diffusion barrier layer(128) is formed on the first upper metallic interconnection pattern. A second upper metallic interconnection layer pattern(124b) fills all inner portion of the trench on the void diffusion barrier layer.

Abstract translation: 目的：提供一种用于防止空隙的金属互连结构和用于互连金属的方法，以通过在空隙的扩散路径上形成通孔接触孔中的空隙扩散阻挡层来提高器件的稳定性。 构成：在第一层间电介质（106）中实现较低的金属互连图案。 金属绝缘层（112）包括露出下部金属互连图案的表面的一部分的通孔接触孔（120a，120b）。 第二层间电介质包括用于暴露金属绝缘层上的通孔接触孔的沟槽。 阻挡金属层（122a，122b）形成在通孔接触孔的侧部和第二下部金属互连图案的暴露表面上。 第一上金属互连图案（124a）填充通孔接触孔和沟槽的一部分。 在第一上金属互连图案上形成空隙扩散阻挡层（128）。 第二上金属互连层图案（124b）填充空隙扩散阻挡层上的沟槽的所有内部部分。

公开(公告)号：KR100446285B1

公开(公告)日：2004-11-16

申请号：KR1019970054197

申请日：1997-10-22

Applicant: 삼성전자주식회사

Inventor： 임헌형 ,  이수근 ,  서태욱

IPC: H01L21/768

Abstract: PURPOSE: A method for forming a trench isolation region is provided to prevent thinning effect of a gate oxide and concentration of electric field to an upper corner of a trench by forming the upper corner of the trench with a round shape. CONSTITUTION: A pad oxide layer pattern(30'), a nitride layer pattern(50'), and an oxide layer pattern are stacked on a semiconductor substrate(10). A trench is formed on the semiconductor substrate. A part of the pad oxide layer pattern and the oxide layer pattern are selectively etched to form a recess on the pad oxide layer pattern and remove the oxide layer pattern. A sidewall oxide layer is formed on the inside of the trench. The trench is buried and an insulating layer is formed on the semiconductor substrate.

公开(公告)号：KR1020040066999A

公开(公告)日：2004-07-30

申请号：KR1020030003935

申请日：2003-01-21

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  이경우

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a dual damascene interconnection pattern of a semiconductor device is provided to prevent or minimize a node separation defect by compensating for a peeled part of the upper part of an interlayer dielectric with a hard mask or a trench opening while using a capping layer. CONSTITUTION: The dual damascene interconnection pattern is formed by using the first and second hard masks. After the second opening for extending the first opening of a via is formed as a trench type. Before a via etch blocking layer gets open, a capping layer(30) for compensating for the peeled portion of the upper part of the interlayer dielectric(8) with the second opening is formed.

Abstract translation: 目的：提供一种用于形成半嵌装置的双镶嵌互连图案的方法，以通过用硬掩模或沟槽开口补偿层间电介质的上部的剥离部分来防止或最小化节点分离缺陷，同时使用 盖层 构成：通过使用第一和第二硬掩模形成双镶嵌互连图案。 在用于延伸通孔的第一开口的第二开口形成沟槽型之后。 在通孔蚀刻阻挡层开放之前，形成用于利用第二开口补偿层间电介质（8）的上部的剥离部分的覆盖层（30）。

公开(公告)号：KR1020040060447A

公开(公告)日：2004-07-06

申请号：KR1020020087245

申请日：2002-12-30

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  이수근 ,  박기철 ,  송원상

IPC: H01L21/28

CPC classification number: H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A metal line of a semiconductor device having a double capping layer and a forming method thereof are provided to prevent the leakage by using the double layer formed with silicon nitride/silicon carbide as a capping layer of a damascene line. CONSTITUTION: A metal line of a semiconductor device having a double capping layer includes an interlayer dielectric, a barrier metal layer, a metal layer, and a double capping layer. A line-shaped groove is formed in the inside of the interlayer dielectric(105). The barrier metal layer(150) is formed on an inner wall of the line-shaped groove. The metal layer is formed on the line-shaped groove on the barrier metal layer. An upper surface of the metal layer is formed in parallel to the upper surface of the interlayer dielectric in order to form a metal line. The double capping layer(190) includes a silicon nitride layer(180) and a silicon carbide layer(185), which are coated on the interlayer dielectric, and the metal layer.

Abstract translation: 目的：提供具有双重覆盖层的半导体器件的金属线及其形成方法，以通过使用由氮化硅/碳化硅形成的双层作为镶嵌线的覆盖层来防止漏电。 构成：具有双层覆盖层的半导体器件的金属线包括层间电介质，阻挡金属层，金属层和双层覆盖层。 在层间电介质（105）的内部形成有线状的槽。 阻挡金属层（150）形成在线状槽的内壁上。 金属层形成在阻挡金属层上的线状槽上。 为了形成金属线，金属层的上表面与层间电介质的上表面平行地形成。 双层覆盖层（190）包括涂覆在层间电介质上的氮化硅层（180）和碳化硅层（185）和金属层。

公开(公告)号：KR1020040013165A

公开(公告)日：2004-02-14

申请号：KR1020020045610

申请日：2002-08-01

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  이경우

IPC: H01L21/28

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877

Abstract: PURPOSE: A method for forming a metal interconnection of a semiconductor device by a modified dual damascene process is provided to avoid a defect of an interconnection by preventing a recess in a via contact of a single damascene structure. CONSTITUTION: The first interlayer dielectric and the first and second material layers are sequentially formed on a semiconductor substrate(100) with a conductive layer(105) such that the first and second material layers include a material that reacts with a medium used in a process for eliminating photoresist. A photoresist layer of a pattern exposing a part of the upper surface of the second material layer is formed on the second material layer. The second material layer, the first material layer and the first interlayer dielectric are etched to form a via hole(160) by using the photoresist layer as an etch barrier layer(110). A part of the first material layer exposed to the via hole is changed while the photoresist layer is eliminated. The changed first material layer(135) is removed to form an opening larger than the via hole in the first material layer. The remaining second material layer is removed. A metal material is deposited to fill the via hole and the opening. A planarization process is performed until the first interlayer dielectric is exposed, so that a via contact is formed.

Abstract translation: 目的：提供通过改进的双镶嵌工艺形成半导体器件的金属互连的方法，以通过防止单个镶嵌结构的通孔接触中的凹陷来避免互连的缺陷。 构成：第一层间电介质和第一和第二材料层依次形成在具有导电层（105）的半导体衬底（100）上，使得第一和第二材料层包括与在工艺中使用的介质反应的材料 用于消除光刻胶。 在第二材料层上形成露出第二材料层的上表面的一部分的图案的光致抗蚀剂层。 通过使用光致抗蚀剂层作为蚀刻阻挡层（110），蚀刻第二材料层，第一材料层和第一层间电介质以形成通孔（160）。 暴露于通孔的第一材料层的一部分在光致抗蚀剂层被消除的同时被改变。 去除改变的第一材料层（135）以形成比第一材料层中的通孔大的开口。 剩余的第二材料层被去除。 沉积金属材料以填充通孔和开口。 进行平坦化处理，直到暴露第一​​层间电介质，从而形成通孔接触。

公开(公告)号：KR1020030061100A

公开(公告)日：2003-07-18

申请号：KR1020020001470

申请日：2002-01-10

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  박기관 ,  이경우

IPC: H01L21/3205

Abstract: PURPOSE: A method for forming an interlayer dielectric pattern is provided to be capable of finely forming an opening portion and securing the vertical profile of the opening portion by using a spacer as an etching mask and using an organic polymer layer as the interlayer dielectric. CONSTITUTION: After forming a conductive layer pattern(110) at the upper portion of a semiconductor substrate, an interlayer dielectric and a hard mask layer are sequentially deposited on the entire surface of the resultant structure. Then, a hard mask pattern having the first opening portion(171) is formed by selectively patterning the hard mask layer for exposing the upper surface of the interlayer dielectric. A spacer(190) is formed at both sidewalls of the first opening portion. The upper surface of the conductive layer pattern is exposed by selectively etching the resultant structure using the spacer as an etching mask. Preferably, the interlayer dielectric is made of at least one selected from a group consisting of an organic polymer layer, a fluorine doped oxide layer, a carbon doped oxide layer, and a silicon oxide layer.

Abstract translation: 目的：提供一种用于形成层间电介质图案的方法，其能够通过使用间隔件作为蚀刻掩模并使用有机聚合物层作为层间电介质来精细地形成开口部分并确保开口部分的垂直轮廓。 构成：在半导体衬底的上部形成导电层图案（110）之后，在所得结构的整个表面上依次沉积层间电介质和硬掩模层。 然后，通过选择性地图案化用于暴露层间电介质的上表面的硬掩模层来形成具有第一开口部分（171）的硬掩模图案。 间隔件（190）形成在第一开口部分的两个侧壁处。 通过使用间隔物作为蚀刻掩模选择性地蚀刻所得到的结构来暴露导电层图案的上表面。 优选地，层间电介质由选自有机聚合物层，掺氟氧化物层，碳掺杂氧化物层和氧化硅层中的至少一种制成。

公开(公告)号：KR1020020088399A

公开(公告)日：2002-11-27

申请号：KR1020020027442

申请日：2002-05-17

Applicant: 삼성전자주식회사

Inventor： 이경우 ,  신홍재 ,  김재학 ,  이수근

IPC: H01L21/28

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76835

Abstract: PURPOSE: A method for forming a metal interconnection layer of a semiconductor device is provided to prevent formation of a metal oxide layer on a conductive layer in a process of removing a photoresist pattern, and prevent an ashing damage and profile fail of a via hole. CONSTITUTION: A stopper layer is formed on a semiconductor substrate. An insulation layer is formed on the stopper layer. A hard mask is formed on the insulation layer. A first photoresist pattern having a first aperture is formed to expose an upper partial portion of the hard mask. A partial via hole having a first width is formed by etching partially the hard mask and the insulation layer with the use of the first photoresist pattern as a mask. The first photoresist pattern is removed. An organic material layer is coated to fill the partial via hole. A second photoresist pattern having a second aperture is formed on the substrate comprised of the organic layer. The organic layer and hard mask layer are etched by using the second photoresist pattern as a mask and the second photoresist pattern and organic layer are removed. An interconnection region having the second width and a via hole having the first width are formed by etching the insulation layer with the use of the hard mask layer as an etch mask.

Abstract translation: 目的：提供一种用于形成半导体器件的金属互连层的方法，以在去除光致抗蚀剂图案的过程中防止在导电层上形成金属氧化物层，并且防止通孔的灰化损坏和轮廓失效。 构成：在半导体衬底上形成阻挡层。 在阻挡层上形成绝缘层。 在绝缘层上形成硬掩模。 形成具有第一孔的第一光致抗蚀剂图案以暴露硬掩模的上部局部部分。 通过使用第一光致抗蚀剂图案作为掩模，部分地蚀刻硬掩模和绝缘层，形成具有第一宽度的部分通孔。 去除第一光致抗蚀剂图案。 涂覆有机材料层以填充部分通孔。 具有第二孔径的第二光致抗蚀剂图案形成在由有机层组成的基板上。 通过使用第二光致抗蚀剂图案作为掩模蚀刻有机层和硬掩模层，并且去除第二光致抗蚀剂图案和有机层。 通过使用硬掩模层作为蚀刻掩模蚀刻绝缘层，形成具有第二宽度的互连区域和具有第一宽度的通孔。

公开(公告)号：KR1020020085722A

公开(公告)日：2002-11-16

申请号：KR1020010025573

申请日：2001-05-10

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  신홍재 ,  이경우 ,  김재학

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: PURPOSE: A metallization method of a semiconductor device is provided to prevent damage of a lower conductive layer when forming a via hole and a trench using dual damascene by using a protection layer made of SOD(Spin On Dielectric). CONSTITUTION: A first etch stopper(410) is formed on a lower conductive layer(300) formed on a semiconductor substrate(100). A first interlayer dielectric(510) and a second etch stopper(450) are sequentially formed on the first etch stopper. A second interlayer dielectric(550) is formed on the second etch stopper. A via hole(710) is formed to expose the lower conductive layer(300) by sequentially etching the second interlayer dielectric(550), the second etch stopper(450) and the first interlayer dielectric(510) using the first etch stopper(410). A protection layer is formed at the bottom of the via hole(710) so as to protect the first etch stopper(410). A trench(750) connected to the via hole is formed by selectively etching the second interlayer dielectric(550) using the second etch stopper(450). After removing the protection layer, the exposed first etch stopper(410) is then removed. Then, an upper conductive layer(900) is formed to fill in the via hole and the trench. At the time, an SOD film, such as HSQ(Hydro SilisesQuioxane) is used as the protection layer.

Abstract translation: 目的：提供半导体器件的金属化方法，以通过使用由SOD（旋转介质）制成的保护层，在使用双镶嵌形成通孔和沟槽时防止下导电层的损坏。 构成：在形成在半导体衬底（100）上的下导电层（300）上形成第一蚀刻停止层（410）。 在第一蚀刻停止器上依次形成第一层间电介质（510）和第二蚀刻停止件（450）。 在第二蚀刻停止件上形成第二层间电介质（550）。 通过使用第一蚀刻停止器（410）依次蚀刻第二层间电介质（550），第二蚀刻停止器（450）和第一层间电介质（510），形成通孔（710）以暴露下导电层（300） ）。 在通孔（710）的底部形成保护层，以保护第一蚀刻停止件（410）。 通过使用第二蚀刻停止器（450）选择性蚀刻第二层间电介质（550）来形成连接到通孔的沟槽（750）。 在去除保护层之后，然后去除暴露的第一蚀刻停止件（410）。 然后，形成上导电层（900）以填充通孔和沟槽。 此时，使用SOD膜，例如HSQ（Hydro SilisesQuioxane）作为保护层。