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公开(公告)号：KR101427954B1
公开(公告)日：2014-08-08
申请号：KR1020120155367
申请日：2012-12-27
Applicant: 현대자동차주식회사
IPC: H01L29/78 , H01L21/336
Abstract: 본 발명의 실시예에 따른 반도체 소자는 n+형 탄화 규소 기판의 제1면에 차례로 배치되어 있는 n-형 에피층, p형 에피층 및 n+ 영역, n+ 영역 및 p형 에피층을 관통하고, 선형의 프로파일을 가지는 제1 부분과 U자 형상의 제2 부분을 포함하는 트렌치, 트렌치 내에 배치되어 있는 게이트 절연막, 게이트 절연막 위에 배치되어 있는 게이트 전극, 게이트 전극 위에 배치되어 있는 산화막, p형 에피층, n+ 영역 및 산화막 위에 배치되어 있는 소스 전극, 그리고 n+형 탄화 규소 기판의 제2면에 위치하는 드레인 전극을 포함하고, 트렌치의 제2 부분은 트렌치의 제1 부분의 아래에 배치되어 있고, 트렌치의 제1 부분의 폭은 트렌치의 제2 부분의 폭보다 더 넓다.
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公开(公告)号：KR101427925B1
公开(公告)日：2014-08-08
申请号：KR1020120129748
申请日：2012-11-15
Applicant: 현대자동차주식회사
IPC: H01L29/78 , H01L21/336 , H01L21/265
Abstract: 본 발명의 실시예에 따른 반도체 소자는 n+형 탄화 규소 기판의 제1면에 위치하는 n형 버퍼층, n형 버퍼층 위에 위치하는 제1 n-형 에피층, 제1 n-형 에피층 위에 위치하는 제2 n-형 에피층, 제1 n-형 에피층 및 제2 n-형 에피층에 위치하는 제1 트렌치 및 제2 트렌치, 제1 트렌치의 하부에서 제1 트렌치의 측벽 안쪽까지 연장되어 있는 p+ 영역, 제2 n-형 에피층 위에 위치하는 n+ 영역, 제2 트렌치 내에 위치하는 게이트 절연막, 게이트 절연막 위에 위치하는 게이트 전극, 게이트 전극 위에 위치하는 산화막, n+ 영역, 산화막 및 p+ 영역 위에 위치하는 소스 전극, 그리고 n+형 탄화 규소 기판의 제2면에 위치하는 드레인 전극을 포함하고, 제1 n-형 에피층의 도핑 농도는 제2 n-형 에피층의 도핑 농도보다 더 높고, 제2 n-형 에피층는 제2 트렌치 양쪽에 각각 위치하고, 제2 n-형 에피층에 채널이 배치되어 있다.
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公开(公告)号：KR1020140079055A
公开(公告)日：2014-06-26
申请号：KR1020120148601
申请日：2012-12-18
Applicant: 현대자동차주식회사
IPC: H01L29/872 , H01L21/329
CPC classification number: H01L29/872 , H01L29/1608 , H01L29/66143 , H01L29/8611
Abstract: A schottky barrier diode according to an embodiment of the present invention includes: an n-type epilayer which is arranged on a first surface of an n+ type silicon carbide substrate; multiple n type pillar regions which are arranged in the n-type epilayer and are arranged on a first part of the first surface of the n+ type silicon carbide substrate; multiple p+ regions in which the n- type epilayer is arranged on the surface, and which are separated from the n type pillar regions; a schottky electrode which is arranged on the n-type epilayer and the p+ regions; and an ohmic electrode which is arranged on a second surface of the n+ type silicon carbide substrate. The doping concentration of the n type pillar regions is greater than the doping concentration of the n- type epilayer.
Abstract translation: 根据本发明实施例的肖特基势垒二极管包括：n型外延层，其布置在n +型碳化硅衬底的第一表面上; 布置在n型外延层中并布置在n +型碳化硅衬底的第一表面的第一部分上的多个n型柱状区域; 多个p +区，其中n型外延层布置在表面上，并且与n型柱区分离; 布置在n型外延层和p +区域上的肖特基电极; 以及设置在n +型碳化硅衬底的第二表面上的欧姆电极。 n型柱区域的掺杂浓度大于n型外延层的掺杂浓度。
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公开(公告)号：KR1020140079027A
公开(公告)日：2014-06-26
申请号：KR1020120148483
申请日：2012-12-18
Applicant: 현대자동차주식회사
IPC: H01L29/872 , H01L21/329
Abstract: A schottky barrier diode according to an embodiment of the present invention includes: an n-type epilayer which is arranged on a first surface of an n+ type silicon carbide substrate; multiple p+ regions which include a first p+ region arranged on the n-type epilayer and a second p+ region arranged on the first p+ region; an n+ type epilayer which is arranged on the n- type epilayer and the first p+ region, and is arranged between the second p+ regions; a schottky electrode which is arranged on the n+ type epilayer and the second p+ region; and an ohmic electrode which is arranged on a second surface of the n+ silicon carbide substrate. The width of the second p+ region is narrower than the width of the first p+ region.
Abstract translation: 根据本发明实施例的肖特基势垒二极管包括：n型外延层，其布置在n +型碳化硅衬底的第一表面上; 包括布置在n型外延层上的第一p +区和布置在第一p +区上的第二p +区的多个p +区; 布置在n型外延层和第一p +区上的n +型外延层，并且布置在第二p +区之间; 布置在n +型外延层和第二p +区域上的肖特基电极; 以及布置在n +碳化硅衬底的第二表面上的欧姆电极。 第二p +区域的宽度比第一p +区域的宽度窄。
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公开(公告)号：KR1020140044075A
公开(公告)日：2014-04-14
申请号：KR1020120110026
申请日：2012-10-04
Applicant: 현대자동차주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/1608 , H01L29/0619 , H01L29/0657 , H01L29/0847 , H01L29/66068 , H01L29/7827 , H01L29/7828
Abstract: A semiconductor device according to an embodiment of the present invention includes an n type buffer layer which is located on the first surface of an n+ type silicon carbide substrate, an n- type epi layer which is located on the n type buffer layer, first and second trenches which are located on the n- type epi layer, an n+ region which is located on the n- type epi layer, a p+ region which is located in the first trench, a gate insulating layer which is located in the second trench, a gate material which is located on the gate insulating layer, an oxide layer which is located on the gate material, a source electrode which is located on the n+ region, the oxide layer, and the p+ region, and a drain electrode which is located on the second surface of the n+ type silicon carbide substrate, wherein multiple first trenches are located in both sides of the second trench, respectively, to be separated from the second trench.
Abstract translation: 根据本发明实施例的半导体器件包括位于n +型碳化硅衬底的第一表面上的n型缓冲层，位于n型缓冲层上的n型外延层，首先和 位于n型外延层上的第二沟槽，位于n型外延层上的n +区，位于第一沟槽中的p +区，位于第二沟槽中的栅极绝缘层， 位于栅极绝缘层上的栅极材料，位于栅极材料上的氧化物层，位于n +区域上的源电极，氧化物层和p +区域，以及位于 在n +型碳化硅衬底的第二表面上，其中多个第一沟槽分别位于第二沟槽的两侧以与第二沟槽分离。
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Patent Agency Ranking
公开(公告)号：KR101382328B1
公开(公告)日：2014-04-08
申请号：KR1020120123011
申请日：2012-11-01
Applicant: 현대자동차주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/1608 , H01L21/0475 , H01L21/049 , H01L29/42356 , H01L29/7827 , H01L29/66068
Abstract: The present invention relates to a method for manufacturing a semiconductor device wherein the method comprises the step of sequentially forming n-type epitaxial layer, p-type epitaxial layer, and a first n+ region at the first surface of n+ type carbon silicon substrate; and the step of forming a trench penetrating the first n+ region and the p-type epitaxial layer and including a first part having a linear profile and elliptical second part wherein the step of forming the trench comprises the step of forming a photosensitive film pattern on the first n+ region; the step of forming the first part of the trench by forming a first trench through etching the first n+ region and p-type epitaxial layer by using the photosensitive film as a mask; the step of forming a buffer layer by using vitreous carbon on the first n+ region and the first trench after removing the photosensitive film pattern; the step of forming a buffer layer pattern by etching the buffer layer for the bottom of the first trench to be exposed; the step of forming a second trench by etching the bottom of the first trench by using the buffer layer pattern as mask; the step of forming the second part of the trench by isotropic etching the second trench; and the step of removing the buffer pattern.
Abstract translation: 本发明涉及一种制造半导体器件的方法，其中该方法包括在n +型碳硅衬底的第一表面上依次形成n型外延层，p型外延层和第一n +区的步骤; 以及形成穿过第一n +区域和p型外延层的沟槽的步骤，并且包括具有线性轮廓和椭圆形第二部分的第一部分，其中形成沟槽的步骤包括以下步骤：在 第n +区; 通过使用感光膜作为掩模，通过蚀刻第一n +区域和p型外延层来形成第一沟槽来形成沟槽的第一部分的步骤; 在去除感光膜图案之后，通过在第一n +区域和第一沟槽上使用玻璃碳形成缓冲层的步骤; 通过蚀刻用于待暴露的第一沟槽的底部的缓冲层来形成缓冲层图案的步骤; 通过使用缓冲层图案作为掩模蚀刻第一沟槽的底部来形成第二沟槽的步骤; 通过各向同性蚀刻第二沟槽形成沟槽的第二部分的步骤; 以及去除缓冲图案的步骤。
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公开(公告)号：KR101261928B1
公开(公告)日：2013-05-08
申请号：KR1020110114977
申请日：2011-11-07
Applicant: 현대자동차주식회사
IPC: H01L29/872
CPC classification number: H01L29/872 , H01L21/046 , H01L21/0495 , H01L29/1608 , H01L29/6606
Abstract: PURPOSE: A method for manufacturing a silicon carbide schottky barrier diode is provided to form a compound oxide layer by thermal oxidation after nitrogen is injected into a wafer surface by using nitrogen plasma, and improve the growth rate of an oxide layer. CONSTITUTION: An n-epi layer(11) is formed on an n+ substrate(10). A compound oxide layer(12) is formed on the n-epi layer. A schottky metal(13) is deposited on the compound oxide layer and the n-epi layer. A pad metal(14) is deposited on the schottky metal. An ohmic metal(15) is deposited in the lower part of the n+ substrate.
Abstract translation: 目的：提供一种制造碳化硅肖特基势垒二极管的方法，通过使用氮等离子体将氮气注入晶片表面之后通过热氧化形成复合氧化物层，并提高氧化物层的生长速率。 构成：在n +衬底（10）上形成n外延层（11）。 复合氧化物层（12）形成在n外延层上。 在复合氧化物层和n外延层上沉积肖特基金属（13）。 垫片金属（14）沉积在肖特基金属上。 在n +衬底的下部沉积欧姆金属（15）。
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公开(公告)号：KR101154674B1
公开(公告)日：2012-06-08
申请号：KR1020100113041
申请日：2010-11-12
Applicant: 현대자동차주식회사
IPC: H01L21/316
Abstract: 본발명의산화막의형성방법은실리콘카바이드웨이퍼상부에플라즈마화학기상증착방법으로 1차전처리공정을수행하여단계와, 상기 1차전처리공정이후유도결합플라즈마화학증착(Inductively Coupled Plasma Chemical Vapor Deposition)방법으로 2차전처리공정을수행하는단계와, 상기 2차전처리공정이후건식산화공정을수행하여산화막을형성하는단계와, 상기산화막에 N어닐링공정을수행하는단계를포함하는것을특징으로한다.
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公开(公告)号：KR1020120051554A
公开(公告)日：2012-05-22
申请号：KR1020100113041
申请日：2010-11-12
Applicant: 현대자동차주식회사
IPC: H01L21/316
CPC classification number: H01L21/02274 , H01L21/28194 , H01L21/324
Abstract: PURPOSE: An oxide film formation method is provided to perform first and second preprocessing processes before performing a dry oxidation process, thereby improving growth rate of an oxide film. CONSTITUTION: A silicon carbide wafer(100) is arranged. A first nitride film(102) is formed on the upper part of the wafer by performing a first preprocessing process. A second nitride film(104) is formed on the upper part of the first nitride film by performing a second preprocessing process. An oxide film(110) is formed by forming a dry oxidation process on the second nitride film. The oxide film comprises a silicon-nitrogen-oxygen(106) film and a silicon oxide film(108). An N2 annealing process(112) is performed on the oxide film.
Abstract translation: 目的：提供氧化膜形成方法，以在进行干燥氧化处理之前进行第一和第二预处理，从而提高氧化膜的生长速度。 构成：设置碳化硅晶片（100）。 通过执行第一预处理工艺，在晶片的上部形成第一氮化物膜（102）。 通过进行第二预处理工艺，在第一氮化物膜的上部形成第二氮化物膜（104）。 通过在第二氮化物膜上形成干式氧化工艺形成氧化膜（110）。 氧化膜包括硅 - 氮 - 氧（106）膜和氧化硅膜（108）。 对氧化膜进行N2退火处理（112）。
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公开(公告)号：KR101776425B1
公开(公告)日：2017-09-08
申请号：KR1020150175661
申请日：2015-12-10
Applicant: 현대자동차주식회사
IPC: H01L23/495 , H01L23/367 , H01L23/40
Abstract: 센터리드프레임을채용하고센터리드프레임의상하에센터리드프레임과전기적인접속을형성하는발열전기소자들을배치함으로써효율적인열 방출이가능한파워모듈이개시된다. 상기파워모듈은, 제1 센터리드프레임; 상기제1 센터리드프레임의상면및 하면에상기제1 센터리드프레임과전기적으로접속되어각각부착된제1 전기소자및 제2 전기소자; 상기제1 전기소자와전기적으로접속되도록상기제1 전기소자의상부에배치되는제1 상부기판; 및상기제2 전기소자와전기적으로접속되도록상기제2 전기소자의하부에배치되는제1 하부기판을포함한다.
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