公开(公告)号：EP1142018B1

公开(公告)日：2008-07-09

申请号：EP99939716.9

申请日：1999-08-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GARDNER, Mark, I. ,  FULFORD, H., Jim

IPC: H01L27/06 ,  H01L21/822

CPC classification number: H01L27/0688 ,  H01L21/8221

Abstract: Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate electrode. A first set of active regions is disposed in portions of the first substrate adjacent the gate electrode and a second set of active regions is disposed above the gate electrode and adjacent the second substrate. The two sets of active regions may be coupled together or used separately.

公开(公告)号：EP1135796B1

公开(公告)日：2006-05-31

申请号：EP99930309.2

申请日：1999-06-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUN, Sey-Ping ,  GARDNER, Mark, I. ,  NGO, Minh, Van

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/3145 ,  H01L21/76828 ,  H01L21/76834

Abstract: An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use un integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deoposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

公开(公告)号：EP1142018A1

公开(公告)日：2001-10-10

申请号：EP99939716.9

申请日：1999-08-09

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： GARDNER, Mark, I. ,  FULFORD, H., Jim

IPC: H01L27/06 ,  H01L21/822

CPC classification number: H01L27/0688 ,  H01L21/8221

Abstract: Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate electrode. A first set of active regions is disposed in portions of the first substrate adjacent the gate electrode and a second set of active regions is disposed above the gate electrode and adjacent the second substrate. The two sets of active regions may be coupled together or used separately.

公开(公告)号：EP1070348A1

公开(公告)日：2001-01-24

申请号：EP98955236.9

申请日：1998-11-02

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： DAWSON, Robert ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/768

CPC classification number: H01L21/76895

Abstract: A local interconnect (LI) structure (112) is formed by forming a silicide layer (60, 50) in selected regions of a semiconductor structure then depositing an essentially uniform layer (110) of transition or refractory metal overlying the semiconductor structure. The metal local interconnect (112) is deposited without forming an intermediate insulating layer between the silicide (60, 50) and metal layers (110) to define contact openings or vias. In some embodiments, titanium is a suitable metal for formation of the local interconnect (112). Suitable selected regions (60) for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions (50). The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etch-stop layer (100) is desired for the patterning of the metal film, a first optional insulating layer (100) is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

公开(公告)号：EP0938752A1

公开(公告)日：1999-09-01

申请号：EP97939764.0

申请日：1997-09-03

Applicant: Advanced Micro Devices, Inc.

Inventor： KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L21 ,  H01L29

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

公开(公告)号：EP0978141B1

公开(公告)日：2006-07-12

申请号：EP98912999.4

申请日：1998-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/8238

CPC classification number: H01L21/823814

Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

公开(公告)号：EP1135796A1

公开(公告)日：2001-09-26

申请号：EP99930309.2

申请日：1999-06-16

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUN, Sey-Ping ,  GARDNER, Mark, I. ,  NGO, Minh, Van

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/3145 ,  H01L21/76828 ,  H01L21/76834

Abstract: An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use un integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deoposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

公开(公告)号：EP1116267A1

公开(公告)日：2001-07-18

申请号：EP99911323.6

申请日：1999-03-12

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： GARDNER, Mark, I. ,  FULFORD, H., Jim ,  MAY, Charles, E.

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66583 ,  H01L21/2652 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66598

Abstract: A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.

公开(公告)号：EP1114447A1

公开(公告)日：2001-07-11

申请号：EP99908423.9

申请日：1999-02-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： GARDNER, Mark, I. ,  FULFORD, H., Jim ,  MAY, Charles, E.

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: Generally, the present invention relates to semiconductor devices having an oxide-nitride gate insulating layer and methods of manufacture thereof. Consistent with the present invention a semiconductor device is formed by forming a nitrogen bearing oxide layer over a substrate and forming a nitride layer over the nitrogen bearing oxide layer. The thickness of the nitride layer is reduced and the nitride layer is annealed in an NH3 bearing ambient. The NH3 anneal may, for example, be performed before or after or while reducing the thickness of the nitride layer. One or more of the gate electrodes may then be formed over the nitride layer using the nitrogen bearing oxide layer and the nitride layer to insulate the gate electrode(s) from the substrate. This technique can, for example, provide a highly reliable and scaled gate insulating layer.

公开(公告)号：EP0797842A1

公开(公告)日：1997-10-01

申请号：EP95942891.0

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, K., Y. ,  GARDNER, Mark, I. ,  HAUSE, Fred

IPC: H01L21

CPC classification number: H01L29/6659 ,  H01L21/823814

Abstract: A method of fabricating a MOS integrated circuit device utilizes high energy, high current implanting of ions through a layer of oxide to form heavily doped source and drain regions which are self-aligned with a polysilicon gate. A thick portion of the oxide layer adjacent to the polysilicon gate prevents heavy doping in the substrate next to the gate. The oxide layer is removed and a liightly doped drain (LDD) implant forms an LDD region which is self-aligned with the gate. Using this method the source/drain and LDD implants are performed using only a single mask and etch operation, rater than two mask and etch operations which are necessary using a conventional process.