公开(公告)号：AU2003293038A1

公开(公告)日：2004-06-18

申请号：AU2003293038

申请日：2003-11-20

Applicant: HRL LAB LLC

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J

IPC: H01L23/58 ,  H01L27/02

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：AU2003278917A1

公开(公告)日：2004-04-19

申请号：AU2003278917

申请日：2003-09-23

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58 ,  G11C7/24 ,  H01L21/285

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

公开(公告)号：AU2002316261A1

公开(公告)日：2003-01-02

申请号：AU2002316261

申请日：2002-06-13

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P

IPC: H01L21/768 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/088

公开(公告)号：AU2002234203A1

公开(公告)日：2002-08-06

申请号：AU2002234203

申请日：2002-01-03

Applicant: HRL LAB LLC

Inventor： BAUKAS JAMES P ,  CLARK WILLIAM M JR ,  CHOW LAP-WAI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L29/76

Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricating such devices.

公开(公告)号：AU2002234201A1

公开(公告)日：2002-08-06

申请号：AU2002234201

申请日：2002-01-03

Applicant: HRL LAB LLC

Inventor： BAUKAS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: H01L23/522 ,  H01L23/58 ,  H01L27/02

Abstract: A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such "trick" via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.

公开(公告)号：WO2004049443A2

公开(公告)日：2004-06-10

申请号：PCT/US0337654

申请日：2003-11-20

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L23/58 ,  H01L27/02

CPC classification number: H01L23/573 ,  H01L27/02 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for and structres for camouflaging an integrated circuit structure. A layer ofconductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract translation: 用于伪装集成电路结构的技术和结构。 设置具有受控轮廓的导电材料层，以在实际上该装置不可操作时提供类似于可操作装置的导电材料的假象边缘。

公开(公告)号：WO02059968B1

公开(公告)日：2003-05-22

申请号：PCT/US0200123

申请日：2002-01-03

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  BAUKAS JAMES P ,  CLARK WILLIAM M JR

Inventor： CHOW LAP-WAI ,  BAUKAS JAMES P ,  CLARK WILLIAM M JR

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprisingmetal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of thecircuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricatingsuch devices.

Abstract translation: 半导体器件，包括集成电路，防止逆向工程，包括导致场氧化物的金属轨迹。 金属化通常导致电路的栅极，源极或漏极区域，而不是绝缘场氧化物，从而误导逆向工程师。 一种用于制造这种装置的方法。

公开(公告)号：WO02059968A3

公开(公告)日：2002-11-14

申请号：PCT/US0200123

申请日：2002-01-03

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  BAUKAS JAMES P ,  CLARK WILLIAM M JR

Inventor： CHOW LAP-WAI ,  BAUKAS JAMES P ,  CLARK WILLIAM M JR

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprisingmetal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of thecircuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricatingsuch devices.

Abstract translation: 半导体器件，包括集成电路，防止逆向工程，包括导致场氧化物的金属轨迹。 金属化通常导致电路的栅极，源极或漏极区域，而不是绝缘场氧化物，从而误导逆向工程师。 一种用于制造这种装置的方法。

公开(公告)号：GB2454418A

公开(公告)日：2009-05-06

申请号：GB0903035

申请日：2007-09-20

Applicant: HRL LAB LLC ,  RAYTHEON CO ,  PROMTEK

Inventor： CLARK WILLIAM M JR ,  CHOW LAP WAI ,  HARBISON GAVIN ,  OUYANG PAUL

IPC: H01L27/02 ,  H01L23/58 ,  H01L29/78

Abstract: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

公开(公告)号：GB2445652B

公开(公告)日：2009-02-25

申请号：GB0724643

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

Abstract: An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.