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    Two-level BCH codes for solid state storage devices
    33.
    发明专利
    Two-level BCH codes for solid state storage devices 未知

    公开(公告)号：GB2492708A

    公开(公告)日：2013-01-09

    申请号：GB201219123

    申请日：2011-03-23

    Applicant: IBM

    Inventor： CIDECIYAN ROY D ,  ELEFTHERIOU EVANGELOS ,  MITTELHOLZER THOMAS

    IPC: G06F11/10 ,  H03M13/15 ,  H03M13/29

    Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage(2)of a solid state storage device(1), where sâ ¥2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub- code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage(2).If each of the first and second codewords comprises N q-ary symbols where q =pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage (2) by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and kâ ¥u, whereby p(k/u)v = s.

    Data management in solid state storage systems
    34.
    发明专利
    Data management in solid state storage systems 未知

    公开(公告)号：GB2488462A

    公开(公告)日：2012-08-29

    申请号：GB201208241

    申请日：2010-12-16

    Applicant: IBM

    Inventor： CIDECIYAN ROY DARON ,  ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAO-YU ,  ILIADIS ILIAS ,  MITTELHOLZER THOMAS

    IPC: G06F11/10

    Abstract: Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage (6) of a solid state storage system (5). Input data is stored in successive groups of data write locations in the solid state storage (6). Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage (6). The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords. The encoding and storage operation is performed such that, in each said group, the encoded input data comprises a plurality of first codewords in each of a plurality of the logical subdivisions and each logical subdivision contains a portion of each of the second codewords for that group.

    Data management in solid state storage devices
    35.
    发明专利
    Data management in solid state storage devices 未知

    公开(公告)号：GB2488457A

    公开(公告)日：2012-08-29

    申请号：GB201207325

    申请日：2010-12-16

    Applicant: IBM

    Inventor： CIDECIYAN ROY DARON ,  ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAO-YU ,  ILIADIS ILIAS

    IPC: G06F11/10

    Abstract: Methods and apparatus are provided for controlling a solid state storage device (5) in which the solid state storage (6) comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage (6). The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage (6), is maintained in memory (13). An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data.

    Container marker scheme for reducing write amplification in solid state devices
    36.
    发明专利
    Container marker scheme for reducing write amplification in solid state devices 未知

    公开(公告)号：GB2485732A

    公开(公告)日：2012-05-23

    申请号：GB201203943

    申请日：2010-09-14

    Applicant: IBM

    Inventor： ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAOYU

    IPC: G11C16/34

    Abstract: A solid state storage device (300) and method are provided. Multiple blocks (310, 315) are configured as storage memory for a solid state storage device (300), and each block includes multiple pages. A controller (305) is configured to operate the solid state storage device (300). A free block (310) of the multiple blocks is assigned a marker level by the controller (305). For a particular page of the multiple pages, each particular page of data is written to a block (300) of the multiple blocks with a marker level corresponding to a level of dynamicity calculated by the controller (305) for that particular page.

    SYNCHRONOUS SERVO CHANNEL FOR LONGITUDINAL POSITION DETECTION AND POSITION ERROR SIGNAL GENERATION IN TAPE DRIVE SYSTEMS
    37.
    发明专利
    SYNCHRONOUS SERVO CHANNEL FOR LONGITUDINAL POSITION DETECTION AND POSITION ERROR SIGNAL GENERATION IN TAPE DRIVE SYSTEMS 未知

    公开(公告)号：CA2636848A1

    公开(公告)日：2007-08-02

    申请号：CA2636848

    申请日：2007-01-10

    Applicant: IBM

    Inventor： HUTCHINS ROBERT ,  JELITTO JENS ,  CHERUBINI GIOVANNI ,  ELEFTHERIOU EVANGELOS

    IPC: G11B5/584

    Abstract: A fully synchronous longitudinal position (LPOS) detection system is provided for improving the reliability of servo channels in tape systems. The system is based on the interpolation of the servo channel output signal, which is sampled by an analog-to-digital converter (ADC) at a fixed sampling rate, using a clock at a nominal frequency, so that interpolated signal samples are obtained at a predetermined fixed rate, independent of tape velocity. This predetermined fixed rate is defined in terms of samples per unit of length, as opposed to samples per unit of time, which is the measure of the ADC sampling rate. The resolution with which the servo channel signal is obtained at the interpolator output is thus determined by the step interpolation distance.

    Maximum transition run (MTR) encoding where prohibited portions of block coded data are replaced with substitute portions
    38.
    发明专利
    Maximum transition run (MTR) encoding where prohibited portions of block coded data are replaced with substitute portions 未知

    公开(公告)号：GB2355165A

    公开(公告)日：2001-04-11

    申请号：GB0016683

    申请日：2000-07-07

    Applicant: IBM

    Inventor： CIDECIYAN ROY D ,  COKER JONATHAN D ,  ELEFTHERIOU EVANGELOS ,  GALBRAITH RICHARD L ,  TRUAX TODD

    IPC: G11B20/14 ,  G11B20/18 ,  H03M5/14 ,  G06F11/10 ,  H03M7/14 ,  H03M7/42 ,  H03M13/01 ,  H03M13/05 ,  H03M13/31 ,  H04L1/00 ,  H04L25/49

    Abstract: Methods and apparatus are provided for encoding a succession of m-bit data words to produce a succession of n-bit code words, where n > m, for supply to a magnetic recording channel. Each m-bit data word is partitioned into a plurality of blocks of bits (5a, 6a, 7a), and at least one of said blocks is encoded (5, 6, 7) in accordance with a block coding scheme such that the resulting bit sequence derived from the m bits of the data word comprises an n-bit sequence (5b, 6b, 7b). An n-bit code word is then produced by at least one stage of violation correction (8,9). The or each stage of violation correction comprises detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations in the n-bit sequence, and replacing any prohibited bit pattern so detected by a respective substitute bit pattern (8b, 9b). The block coding scheme and the prohibited and substitute bit patterns are predetermined such that, in a succession of said n-bit code words, the maximum number of consecutive bits of one value is limited to a first predetermined number j, where j / 2, and the maximum number of consecutive bits of the other value is limited to a second predetermined number k.

    39.
    发明专利
    未知

    公开(公告)号：DE69412288D1

    公开(公告)日：1998-09-10

    申请号：DE69412288

    申请日：1994-02-10

    Applicant: IBM

    Inventor： ELEFTHERIOU EVANGELOS ,  PETERSEN BRENT

    IPC: H04B1/7103 ,  H04B3/06 ,  H04B7/26 ,  H04J13/00 ,  H04L25/03

    Abstract: PCT No. PCT/EP94/00374 Sec. 371 Date Jun. 27, 1996 Sec. 102(e) Date Jun. 27, 1996 PCT Filed Feb. 10, 1994 PCT Pub. No. WO95/22209 PCT Pub. Date Aug. 17, 1995The present invention concerns an apparatus and method for reducing the multiuser-interference of input signals. The apparatus in accordance with the present invention comprises a multivariate predictor (81) and a decision quantizer (82), said multivariate predictor (81) operating on interference signals +E,uns eta +EE '(D) provided by means for extracting interference signals (83), said interference signals +E,uns eta +EE '(D) being obtained from said input signals and output signals +E,cir +E,uns b+EE +EE (D) which are available at an output of said decision quantizer (82) and fed back from there to said means for extracting interference signals (83).

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