公开(公告)号：CA2437039A1

公开(公告)日：2002-10-24

申请号：CA2437039

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHIU GEORGE L ,  TAKKEN TODD E ,  CIPOLLA THOMAS M ,  CHEN DONG ,  MOK LAWRENCE S ,  COTEUS PAUL W ,  GARA ALAN G ,  KOPSCAY GERALD V ,  HEIDELBERGER PHILIP ,  GIAMPAPA MARK E

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/16 ,  G06F15/00

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includ es node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes (20) are interconnected by multiple independent networks (26) that optimally maximizes packet communications throughput and minimizes latency. The multiple networks may include three high-speed networ ks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance.

公开(公告)号：AU2002252085A1

公开(公告)日：2002-09-12

申请号：AU2002252085

申请日：2002-02-25

Applicant: IBM

Inventor： GIAMPAPA MARK E ,  TAKKEN TODD E ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/16

Abstract: In a massively parallel system, a method and apparatus for uniquely assigning a MAC address(400) to a device encodes the MAC address with a physical location of the device(410). The method and apparatus include configuring device interconnections of the parallel system with physical topological information such as a rack number, a midplane number, a card number, and a chip number. A device or node with a physical location encoded MAC address may then be interrogated by location for test, diagnostic, and program loading purposes.

公开(公告)号：CA2437036A1

公开(公告)日：2002-09-06

申请号：CA2437036

申请日：2002-02-25

Applicant: IBM

Inventor： VRANAS PAVLOS M ,  STEINMACHER-BUROW BURKHARD D ,  GARA ALAN G ,  CHEN DONG ,  BHANOT GYAN V ,  HEIDELBERGER PHILIP ,  GIAMPAPA MARK E

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: The present invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transfor m (FFT) of a multidimensional array comprising a plurality of elements initial ly distributed in a multi-node computer system(100) comprising a plurality of nodes(Q11-Q33) in communication over a network, comprising distributing the plurali ty of elements of the array in a first dimension across the pluralit y of nodes of the computer system over the network to facilitate a first one- dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing t he one-dimensional FFT-transformed elements at each node in a second dimension via "all-to-all" distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FF T on elements of the array re-distributed at each node in the second dimension , wherein the random order facilitated efficient utilization of the network thereby efficiently implementing the multidimensional FFT. The "all-to-all" re- distribution of the array elements is further efficiently implemented in applications other that the multidimensional FFT on the distributed-memory parallel supercomputer.

公开(公告)号：CA2437035A1

公开(公告)日：2002-09-06

申请号：CA2437035

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  GARA ALAN G ,  TAKKEN TODD E ,  BLUMRICH MATTHIAS A ,  COTEUS PAUL W ,  HEIDELBERGER PHILIP ,  KOPSCAY GERARD V ,  STEINMACHER-BUROW BURKHARD D ,  GIAMPAPA MARK E

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/00 ,  G06F15/76

Abstract: A system and method for generating global asynchronous signals in a computin g structure. Particularly, a global interrupt and barrier network is implement ed that implements logic for generating global interrupt and barrier signals fo r controlling global asynchronous operations perfomed by processing elements a t selected processing nodes (12) of computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes (12) for communicating the global interrupt and barrier signals to the elements via low latency paths. The global asynchronous signa ls respectively initiate interrupt and barrier operations at the processing nod es (12) at times selected for otpimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structur e comprising a plurality of processing nodes interconnected by multiple independent networks.

公开(公告)号：DE10003376A1

公开(公告)日：2000-08-03

申请号：DE10003376

申请日：2000-01-26

Applicant: IBM

Inventor： ABALI BULENT ,  FRANKE HUBERTUS ,  GIAMPAPA MARK E

IPC: G06F3/14 ,  G06F3/048 ,  G06F5/01 ,  G06F5/06 ,  G09G5/00 ,  G09G5/34 ,  H04N5/228

Abstract: The device has a measurement sensor (41H,41V) for measuring movement of the display unit (100) and a motion compensation circuit that is functionally connected to the sensor to compensate for the movements of the display unit so that the image remains essentially stationary on the screen of the display unit in relation to an observer. An Independent claim is also included for a method of image stabilization in a display unit.

公开(公告)号：CA2102878A1

公开(公告)日：1994-09-03

申请号：CA2102878

申请日：1993-11-10

Applicant: IBM

Inventor： FITCH BLAKE G ,  GIAMPAPA MARK E ,  JOSEPH DOUGLAS J

IPC: H04L12/56

Abstract: A message packet transmitter for transmitting a packet of electronic data signals onto a communication network without interruption. A first-in, first-out electronic memory has a transmit state in which an electronic data signal stored therein is output. The electronic memory has an idle state in which electronic data signals stored therein are not output. A message packet-in-transit identification circuit generates a packet-in-transit signal after the electronic memory outputs the first electronic data signal in a message packet. A no-packet-in-transit signal is generated after the electronic memory outputs the last electronic data signal in the message packet. A state controller maintains the electronic memory in the transmit state when the electronic memory stores at least a portion of a message packet, when the state controller receives a packet-in-transit signal, and when the state controller receives an interrupt-pending signal.