公开(公告)号：CA981370A

公开(公告)日：1976-01-06

申请号：CA146795

申请日：1972-07-11

Applicant: IBM

Inventor： BOGER KLAUS ,  GENG HELLMUTH R ,  GOETZE VOLKMAR ,  HAJDU JOHANN

IPC: G06F12/10

Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

公开(公告)号：DE2237925A1

公开(公告)日：1974-02-21

申请号：DE2237925

申请日：1972-08-02

Applicant: IBM DEUTSCHLAND

Inventor： LAMPE HANS ,  POHLE WERNER ,  RUDOLPH PETER ,  SIMONINI FRANCO ,  FRITZSCH KURT ,  KOEDERITZ FRITZ ,  REICHL LEOPOLD DIPL ING ,  BLUM ARNOLD DIPL ING ,  MOHR CLAUS DR ,  HAJDU JOHANN ,  GOETZE VOLKMAR DIPL ING ,  GENG HELLMUTH

IPC: G06F11/14 ,  G06F11/273 ,  G06F11/00

公开(公告)号：DE2131787A1

公开(公告)日：1973-01-11

申请号：DE2131787

申请日：1971-06-26

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  SKUIN PETAR ,  VOGT EDWIN DR ,  ROLAND GENG HELLMUTH

IPC: G06F11/08 ,  G06F11/10 ,  H04L1/00 ,  H03K13/32

Abstract: In a data processing system, a first processing unit is connected to several other processing units by one transfer bus each for the two directions of transmission, a circuit arrangement for error detection being associated with the transfer lines. The first unit comprises a check character generator generating a parity check character both for the information to be transferred from the first processing unit to the further processing units and from the further processing units to the first processing unit. The transfer lines of both directions are provided with a common transfer path, by means of which the parity check characters generated by the check character generator are transferred from the first unit to the further units. Each of the further units comprises a check circuit connected to the two transfer buses and the check character transfer path and checking the correctness of the transferred information for both directions of transmission.

公开(公告)号：DE1935258A1

公开(公告)日：1971-01-14

申请号：DE1935258

申请日：1969-07-11

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER ,  REICHL LEOPOLD ,  EDWIN VOGT DIPL-ING DR ,  PAINKE HELMUT

IPC: G06F9/46 ,  G06F9/48