-
公开(公告)号：DE60203380T2
公开(公告)日：2006-02-02
申请号：DE60203380
申请日：2002-01-28
Applicant: IBM
Inventor： BASSO CLAUDE , CALVIGNAC LOUIS , HEDDES MARCO , LOGAN FRANKLIN , VERPLANKEN JEAN
Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
-
公开(公告)号：AT300763T
公开(公告)日：2005-08-15
申请号：AT02708513
申请日：2002-03-28
Applicant: IBM , CIT ALCATEL
Inventor： BARRI PETER , CALVIGNAC JEAN , HEDDES MARCO , LOGAN JOSEPH , NIEMEGEERS ALEX , VERPLANKEN FABRICE , VRANA MIROSLAV
Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
-
公开(公告)号：ES2237667T3
公开(公告)日：2005-08-01
申请号：ES02712095
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L29/06 , H04L12/56
Abstract: Un sistema que comprende: - un procesador (100) configurado para tratar cuadros de datos, cuyo procesador comprende: - una unidad (110) de flujo de datos configurada para recibir y transmitir dichos cuadros de datos, y en la que cada uno de dichos cuadros de datos tiene un bloque de control de cuadro asociado, y cada uno de dichos bloques de control de cuadro comprende unos bloques de control primero y segundo; - una primera memoria (210) acoplada a dicha unidad de flujo de datos, cuya primera memoria comprende una primera unidad de control de memoria intermedia de cuadro, y dicha primera unidad de control de memoria intermedia de cuadro almacena información de campo para dicho primer bloque de control de dicho bloque de control de cuadro; y - un planificador de ejecución (130) acoplado a dicha unidad de flujo de datos, cuyo planificador está configurado para planificar cuadros de datos recibidos por dicha unidad de flujo de datos, y en el que dicho planificador comprende una segunda memoria (224), la cual comprende una segunda unidad de control de memoria intermedia de cuadro, y dicha segunda unidad de control de memoria intermedia de cuadro almacena información de campo para dicho segundo bloque de control del citado bloque de control de cuadro.
-
公开(公告)号：MY118288A
公开(公告)日：2004-09-30
申请号：MYPI9702506
申请日：1997-06-05
Applicant: IBM
Inventor： COLMANT MICHEL , ENGBERSEN ANTONIUS P , HEDDES MARCO , WEERT MARINUS J M VAN
IPC: H04Q3/00 , H04L12/54 , H04L12/70 , H04L12/933 , H04Q11/04
Abstract: THE INVENTION RELATES TO A SWITCHING DEVICE WHICH TRANSPORTS DATA PACKETS FROM INPUT PORTS (101-108)TO SELECTED OUTPUT PORTS(501-508). THE PAYLOAD OF THE PACKETS IS STORED IN A STORAGE MEANS. A SWITCHING MEANS (3401-3432)IS ARRANGED WHICH HAS MORE SWITCH OUTPUTS (291-294)THAN SWITCH INPUTS (85)AND WHICH SWITCHES SEQUENTIALLY BETWEEN ONE SWITCH INPUT AND SEVERAL SWITCH OUTPUTS WHILE STORING THE PAYLOADS. FURTHERMORE, THE INVENTION RELATES TO A STORING METHOD WHICH USES SWITCHING MEANS TO STORE PAYLOADS IN A SEQUENTIAL ORDER AND TO A SWITCHING APPARATUS COMPRISING SEVERAL SWITCHING DEVICES. FURTHERMORE, THE INVENTION RELATES TO SYSTEMS USING THE SWITCHING DEVICE AS A SCALEABLE MODULE.
-
公开(公告)号：PL355786A1
公开(公告)日：2004-05-17
申请号：PL35578600
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVID GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
-
Patent Agency Ranking
公开(公告)号：CZ20021442A3
公开(公告)日：2002-07-17
申请号：CZ20021442
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
-
37.发明专利
公开(公告)号：AU4430901A
公开(公告)日：2001-10-30
申请号：AU4430901
申请日：2001-03-26
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
-
公开(公告)号：DE69130392D1
公开(公告)日：1998-11-26
申请号：DE69130392
申请日：1991-07-10
Applicant: IBM
Inventor： LUIJTEN RONALD P , HEDDES MARCO
Abstract: The present invention relates to the management of a large and fast memory. The memory is logically subdivided into several smaller parts called buffers. A buffer-control memory (11) having as many sections for buffer-control records as buffers exist is employed together with a buffer manager (12). The buffer manager (12) organizes and controls the buffers by keeping the corresponding buffer-control records in linked lists. A request manager (20), as part of the buffer manager (12), does or does not grant the allocation of a buffer. A stack manager (21) controls the free buffers by keeping the buffer-control records in a stack (23.1), and a FIFO manager (22) keeps the buffer-control records of allocated buffers in FIFO linked lists (23.2 - 23.n). The stack and FIFO managers (20), (21) are parts of the buffer manager (12), too.
-
公开(公告)号：AT435556T
公开(公告)日：2009-07-15
申请号：AT00976194
申请日：2000-11-21
Applicant: IBM
Inventor： AYDEMIR METIN , BASS BRIAN , JEFFRIES CLARK , ROVNER SONIA , SIEGEL MICHAEL , GALLO ANTHONY , GORTI BRAHMANAND , HEDDES MARCO
IPC: H04L47/30
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
-
公开(公告)号：DE60132437T2
公开(公告)日：2009-01-08
申请号：DE60132437
申请日：2001-03-26
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
-
-
-
-
-
-
-
-
-
Search Results
65
records
(took 0.045 seconds)
