公开(公告)号：AU2017392846B2

公开(公告)日：2020-09-17

申请号：AU2017392846

申请日：2017-12-15

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  SCHMIDT DONALD WILLIAM ,  JACOBI CHRISTIAN ,  SAPORITO ANTHONY ,  ROSA DANIEL

IPC: G06F9/48 ,  G06F9/50

Abstract: A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.

公开(公告)号：CA3127864A1

公开(公告)日：2020-08-06

申请号：CA3127864

申请日：2020-01-23

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  SOFIA ANTHONY THOMAS ,  KLEIN MATTHIAS ,  WEISHAUPT SIMON ,  FARRELL MARK ,  SLEGEL TIMOTHY ,  MISHRA ASHUTOSH ,  JACOBI CHRISTIAN

IPC: G06F9/30

Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

公开(公告)号：CA3127840A1

公开(公告)日：2020-08-06

申请号：CA3127840

申请日：2020-01-14

Applicant: IBM

Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

IPC: G06F9/30 ,  G06F13/20

Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

公开(公告)号：CA3118174A1

公开(公告)日：2020-05-14

申请号：CA3118174

申请日：2019-11-05

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  RECKTENWALD MARTIN ,  SCHMIDT DONALD WILLIAM ,  SLEGEL TIMOTHY ,  PURANIK ADITYA NITIN ,  FARRELL MARK ,  JACOBI CHRISTIAN ,  BRADBURY JONATHAN ,  ZOELLIN CHRISTIAN GERHARD

IPC: G06F9/30 ,  G06F9/38

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：CA2874181C

公开(公告)日：2020-03-24

申请号：CA2874181

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F9/30 ,  G06F12/00

Abstract: Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt.

公开(公告)号：CA2874179C

公开(公告)日：2020-02-18

申请号：CA2874179

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/30 ,  G06F9/312

Abstract: A transaction begin instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

公开(公告)号：CA2874178C

公开(公告)日：2020-02-18

申请号：CA2874178

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F9/30 ,  G06F9/48

Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

公开(公告)号：CA2867116C

公开(公告)日：2020-02-18

申请号：CA2867116

申请日：2012-11-15

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F9/34

Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

公开(公告)号：DE112018002032T5

公开(公告)日：2020-01-16

申请号：DE112018002032

申请日：2018-06-14

Applicant: IBM

Inventor： RECKTENWALD MARTIN ,  JACOBI CHRISTIAN ,  REICHART JOHANNES CHRISTIAN ,  HELMS MARKUS MICHAEL

IPC: G06F12/08

Abstract: Hierin offenbart ist ein virtuelles Cacheverzeichnis in einem Prozessor, der Adressübersetzungen beseitigt, wenn die virtuelle Adresse und die reale Adresse in dem Cacheverzeichnis dieselben sind. Der Prozessor ist konfiguriert, virtuellen Speicher und mehrere Threads zu unterstützen. Das virtuelle Cacheverzeichnis enthält eine Mehrzahl von Verzeichniseinträgen, jeder Eintrag ist einer Cachezeile zugeordnet. Jede Cachezeile besitzt ein Tag. Das Tag enthält eine logische Adresse, eine Adressraumkennung, einen Bitanzeiger einer realen Adresse und einen Anzeiger von virtueller Adresse zu realer Adresse. Dieser Anzeiger von virtueller Adresse zu realer Adresse zeigt an, ob die logische Adresse und die reale Adresse dieselben sind. Bei Aktivierung wird keine Adressübersetzung durchgeführt.

公开(公告)号：DE112018002028T5

公开(公告)日：2020-01-16

申请号：DE112018002028

申请日：2018-06-14

Applicant: IBM

Inventor： RECKTENWALD MARTIN ,  SAPORITO ANTHONY ,  JACOBI CHRISTIAN ,  TSAI AARON ,  REICHART JOHANNES CHRISTIAN ,  HELMS MARKUS MICHAEL ,  MAYER ULRICH

IPC: G06F12/08

Abstract: Offenbart hierin ist ein virtueller Cache und ein Verfahren in einem Prozessor zur Unterstützung von mehreren Threads auf derselben Cachezeile. Der Prozessor ist so konfiguriert, dass er einen virtuellen Speicher und mehrere Threads unterstützt. Das virtuelle Cacheverzeichnis enthält eine Vielzahl von Verzeichniseinträgen, wobei jeder Eintrag zu einer Cachezeile gehört. Jede Cachezeile hat ein entsprechendes Tag. Das Tag enthält eine logische Adresse, eine Adressraumkennung, einen Bitanzeiger für eine reale Adresse und ein threadweises Gültigkeitsbit für jeden Thread, der auf die Cachezeile zugreift. Wenn ein nachfolgender Thread feststellt, dass die Cachezeile für diesen Thread gültig ist, wird das Gültigkeitsbit für diesen Thread gesetzt, während beliebige Gültigkeitsbits für andere Threads nicht ungültig gemacht werden.