公开(公告)号：DE102005019041A1

公开(公告)日：2006-11-02

申请号：DE102005019041

申请日：2005-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  PLAETTNER ECKEHARD ,  WEIS CHRISTIAN ,  JAKOBS ANDREAS

IPC: G11C7/22 ,  G11C11/4076

Abstract: The method involves transmitting a write instruction signal synchronized to a clock signal in memory circuits, and transmitting a write data signal that is synchronized to a strobe signal. A phase misalignment between the transmitted clock signal and the transmitted strobe signal is adjusted, and a write acceptance signal is generated depending on the clock signal and the write instruction signal with preset pulse duration. A number of edges of the strobe signals are determined, during the pulse duration. An independent claim is also included for a memory system with a memory circuit and a memory controller.

公开(公告)号：DE50110202D1

公开(公告)日：2006-08-03

申请号：DE50110202

申请日：2001-04-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ

IPC: G11C11/22 ,  G11C7/06

Abstract: A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.

公开(公告)号：DE10008243B4

公开(公告)日：2005-09-22

申请号：DE10008243

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  G11C8/00

Abstract: An integrated storage device has storage cells (MC) which are arranged at the crossing points of word-lines (WLi), bit- lines (BLi) and board conductor segments (PLi). The storage/memory capacitors (C) each have a first electrode which is connected to the board conductor segments (PLi) and a second electrode which is connected via the associated selection transistor (T) to one of the bit-lines (BLi). The selection transistors (T) each have a control terminal which is connected with one of the word-lines (WLi). The bit-lines (BLi) are combined to form columns (BL0..3, BL4..7) which can be selected via column selection lines (CSLi), and a column encoder (CDEC) is provided for controlling the column selection lines (CSLi) depending on the column address (CADR). A line encoder (RDEC) is provided for controlling the word-lines (WLi) depending on the word address (WADR). Driver units (DRVi) generate potentials which have a definite value for each operating state of the storage device, depending on the potentials of the word addresses (RDAR) on the board conductor segments connected to them, as well as on the potentials of the associated column selection lines (CSLi), and are connected via the column selection lines (CSLi) to the board conductor segments (PLi).

公开(公告)号：DE10245536B4

公开(公告)日：2005-02-03

申请号：DE10245536

申请日：2002-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  RUCKERBAUER HERMANN ,  MUFF SIMON

IPC: G01R35/00 ,  G06F11/24 ,  G06F11/27 ,  G06F13/38 ,  G11C7/10 ,  G11C29/02 ,  H04L7/04

公开(公告)号：DE10255872B4

公开(公告)日：2004-09-30

申请号：DE10255872

申请日：2002-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  BRAUN GEORG

IPC: G11C7/10 ,  G11C29/00 ,  G11C7/00

Abstract: The memory module (1) has a number of data storage devices (2) for storage of useful data, coupled via data lines (5) with at least one buffer for the data signals transferred between the data storage devices and a memory control. An integrated buffer and fault control module (7) is incorporated in a common component housing with at least one data storage device. Also included are Independent claims for the following: (a) a buffer and fault control module for a memory module; (b) an operating method for data storage devices of a memory module; (c) an optimizing method for a storage control device of a memory module

公开(公告)号：DE10255872A1

公开(公告)日：2004-06-24

申请号：DE10255872

申请日：2002-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  BRAUN GEORG

IPC: G11C7/10 ,  G11C29/00 ,  G11C7/00

Abstract: The memory module (1) has a number of data storage devices (2) for storage of useful data, coupled via data lines (5) with at least one buffer for the data signals transferred between the data storage devices and a memory control. An integrated buffer and fault control module (7) is incorporated in a common component housing with at least one data storage device. Also included are Independent claims for the following: (a) a buffer and fault control module for a memory module; (b) an operating method for data storage devices of a memory module; (c) an optimizing method for a storage control device of a memory module

公开(公告)号：DE10245248A1

公开(公告)日：2004-04-08

申请号：DE10245248

申请日：2002-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIEHL OLIVER ,  BRAUN GEORG ,  RUCKERBAUER HERMANN

IPC: G11C7/10 ,  G11C11/4093 ,  G11C7/00

Abstract: Memory parameter devices have lasting storage for the features of a semiconductor/dual in-line memory module (DIMM) (3) and are programmable e-fuses that fit on each semiconductor memory component/dynamic (DRAM) or static/shadow (SRAM) RAM component (11,12 ... 1n) and are in a closed or non-closed condition corresponding to stored parameter data. Independent claims are also included for the following: (a) A semiconductor component like dynamic RAM or static/shadow RAM for use on the semiconductor memory module; (b) and for a semiconductor memory system with a semiconductor memory module.

公开(公告)号：DE59905208D1

公开(公告)日：2003-05-28

申请号：DE59905208

申请日：1999-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RONNY ,  BRAUN GEORG

IPC: G11C11/22

Abstract: The memory device has series-connected ferroelectric memory cells in which a series circuit composed of a resistor and/or of a transistor for the ferroelectric capacitor of a respective memory cell is present. As a result, without unacceptably increasing the access time, the interference pulses at the ferroelectric capacitors of the memory cells which are not being addressed at that particular time and which are generated by the reading out or writing of the addressed memory cell are reduced in such a way that they have virtually no further influence on the non-addressed memory cells.

公开(公告)号：DE10146491A1

公开(公告)日：2003-04-24

申请号：DE10146491

申请日：2001-09-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  BRAUN GEORG

IPC: H03K19/00 ,  H04L25/06 ,  H04L12/40 ,  H04B3/04

Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.

公开(公告)号：DE19832994C2

公开(公告)日：2003-02-13

申请号：DE19832994

申请日：1998-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/108

Abstract: A ferroelectric storage assembly containing a storage cell array composed of a plurality of storage cells is described. Each storage cell contains at least one selector transistor and a storage capacitor, and can be controlled via word lines and bit lines. A short-circuit transistor is located over each storage capacitor in order to protect the storage.