公开(公告)号：DE10162542A1

公开(公告)日：2003-04-10

申请号：DE10162542

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STADLER WOLFGANG ,  BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  STREIBL MARTIN ,  WENDEL MARTIN ,  RIESS PHILIPP

IPC: H01L23/544 ,  H01L23/60 ,  H01L21/66

Abstract: The method involves common production of an integrated circuit and a test structure using the same process steps, measuring electrical parameters on the test structure, driving characteristic values from the measured parameter values that characterize an electrostatic discharge/latch-up characteristic of the integrated circuit and checking whether they are in a define range selected to achieve desired electrostatic discharge/latch-up behavior.

公开(公告)号：DE102015107680A1

公开(公告)日：2016-11-17

申请号：DE102015107680

申请日：2015-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESMARK KAI ,  DIBRA DONALD ,  CAO YIQUN

IPC: H01L23/60 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78

Abstract: Eine Ausführungsform einer integrierten Schaltung weist eine minimale laterale Abmessung (dm) einer Halbleiterwanne (102) an einer ersten Oberfläche (104) eines Halbleiterkörpers (106) auf. Die integrierte Schaltung umfasst zudem einen ersten lateralen DMOSFET, der einen Lastpfad (110) aufweist, welcher mit einem Lastpin (112) elektrisch gekoppelt ist. Der erste laterale DMOSFET eignet sich dazu, einen Laststrom durch ein Lastelement (114), das mit dem Lastpin (112) elektrisch gekoppelt ist, zu steuern. Eine minimale laterale Abmessung (d) eines Draingebiets (116) des ersten lateralen DMOSFET an der ersten Oberfläche (104) des Halbleiterkörpers (106) ist um mehr als 50% größer als die minimale laterale Abmessung (dm).

公开(公告)号：DE102008005932B4

公开(公告)日：2011-02-24

申请号：DE102008005932

申请日：2008-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSS CORNELIUS CHRISTIAN ,  ESMARK KAI ,  ALVAREZ DAVID ,  SCHNEIDER JENS

IPC: H01L23/60 ,  H01L29/06

公开(公告)号：DE102008059848A1

公开(公告)日：2009-08-13

申请号：DE102008059848

申请日：2008-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESMARK KAI ,  SCHNEIDER JENS ,  WENDEL MARTIN

IPC: H01L29/866 ,  H01L21/822 ,  H01L23/60

公开(公告)号：DE10255359B4

公开(公告)日：2008-09-04

申请号：DE10255359

申请日：2002-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENDEL MARTIN ,  STREIBL MARTIN ,  ESMARK KAI ,  RIESS PHILIPP ,  SCHAFBAUER THOMAS

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

公开(公告)号：DE102005056908B4

公开(公告)日：2008-02-28

申请号：DE102005056908

申请日：2005-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLASER ULRICH ,  GOSNER HARALD ,  ESMARK KAI

IPC: H01L23/60 ,  H01L27/08 ,  H01L29/74

Abstract: An integrated circuit comprises a p-doped anode (16) and a separated n-doped cathode (22) in a substrate (11) with a less n- and p- doped inner region (18,20) adjacent to the anode. There are maximally doped n and p tubs (26) and the maximum concentration of dopant in the n- and p- inner regions in the direction away from the substrate surface remains beneath that of the tubs. An independent claim is also included for a production process for the above integrated circuit.

公开(公告)号：DE102005056908A1

公开(公告)日：2007-05-31

申请号：DE102005056908

申请日：2005-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLASER ULRICH ,  GOSNER HARALD ,  ESMARK KAI

IPC: H01L23/60 ,  H01L27/08 ,  H01L29/74

Abstract: An integrated circuit comprises a p-doped anode (16) and a separated n-doped cathode (22) in a substrate (11) with a less n- and p- doped inner region (18,20) adjacent to the anode. There are maximally doped n and p tubs (26) and the maximum concentration of dopant in the n- and p- inner regions in the direction away from the substrate surface remains beneath that of the tubs. An independent claim is also included for a production process for the above integrated circuit.

公开(公告)号：DE10255130B4

公开(公告)日：2007-03-22

申请号：DE10255130

申请日：2002-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STREIBL MARTIN ,  ESMARK KAI ,  WENDEL MARTIN ,  STADLER WOLFGANG ,  GOSNER HARALD

IPC: H01L23/60 ,  H02H9/04

公开(公告)号：DE102005013478A1

公开(公告)日：2006-10-05

申请号：DE102005013478

申请日：2005-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STREIBL MARTIN ,  ESMARK KAI

IPC: H01L23/60 ,  H01L23/36

Abstract: The method involves discharging an over voltage adjoining a semiconductor circuit, over a discharge path by an electrostatic discharge (ESD) protection device (1). A contact hole (8) and a metal layer (9) are arranged in the device for heat conduction, and have a heat conductivity higher than the average heat conductivity of the materials of the circuit. The hole and the metal layer are arranged close to hotspots of the device. An independent claim is also included for a semiconductor circuit comprising an ESD protection device.

公开(公告)号：DE102004009981B4

公开(公告)日：2005-12-29

申请号：DE102004009981

申请日：2004-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STREIBL MARTIN ,  ESMARK KAI ,  RUSS CHRISTIAN ,  WENDEL MARTIN ,  GOSNER HARALD

IPC: H01L23/60 ,  H02H9/00 ,  H02H9/02

Abstract: An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor structure and one ESD protective element between two supply networks. The emitter of the bipolar transistor structure is electrically connected to the input or output, while the base is electrically connected to one of the two supply networks. The collector produces a current signal, which is used for triggering of the ESD protective element, when an ESD load occurs at the input or output.