Abstract:
PROBLEM TO BE SOLVED: To secure electrostatic discharge protection in an electric circuit and to also reduce a size. SOLUTION: The gate-controlled fin-type resistive element to be used as the electrostatic discharge protection element in the electric circuit includes a fin structure having a first terminal region, a second terminal region, and a channel region formed between the first terminal region and second terminal region. The fin-type resistive element includes a gate region formed at least on a portion of an upper surface of the channel region. The gate region is electrically coupled to the gate control part. The gate control part controls an electrical potential applied on the gate region to increase electrical resistance of the gate-controlled fin-type resistive element when the electrical circuit is in a first operation state, and to lower the electrical resistance in a second operation state characterized by a start of an electrostatic discharge phenomenon. COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a miniaturized electric circuit in which a protection of an electric discharge is assured. SOLUTION: A fin-type resistance element gate-controlled for being used as an electrostatic discharge protection element in an electric circuit comprises a fin structure having a first terminal region, a second terminal region, and a channel region formed between the first and second terminal regions. The fin-type resistance element further comprises a gate region formed on at least a part of an upper surface of the channel region. The gate region is electrically connected to a gate controlling part. By controlling an electric potential applied to the gate region, the gate controlling part makes an electric resistance of the gate-controlled fin-type resistance element light while the electric circuit is in a first operation state, and the gate controlling part lowers the electric resistance while the electric circuit is in a second operation state characterized by the start of an electrostatic discharge phenomenon. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
The invention relates to a circuit arrangement (10) that comprises a capacitor (12) inside an n-trough (20). A specific polarization of the capacitor (12) makes sure that a depletion zone is formed in the trough (20) and the capacitor (12) has a high ESD resistance. An optionally present auxiliary doped layer (26) ensures a high area capacitance of the capacitor despite high ESD resistance.
Abstract:
The fin-type bipolar transistor has a fin structure that is formed in the main region of transistor. A terminal region is formed on a portion of main region such that the terminal region is formed as an epitaxially grown region. Independent claims are included for the following: (1) method for producing bipolar transistor; (2) vertically integrated electronic device; (3) method for producing vertically integrated electronic device; (4) bipolar complementary metal oxide semiconductor (BiCMOS) circuit arrangement; and (5) method for fabricating BiCMOS circuit arrangement.
Abstract:
A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.
Abstract:
An electronic circuit (100) comprises at least one circuit (101) comprising at least one multi-gate functional FET (102) with at least two gates and at least one ESD protection circuit (103) comprising a multi-gate protective FET (104) that is formed partly as an electrical charge carrying reducing transistor. The trigger voltage of the protective FET is less than that of the functional FET. Independent claims are also included for the following: (A) A circuit arrangement as above;and (B) A production process for the above.
Abstract:
An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor structure and one ESD protective element between two supply networks. The emitter of the bipolar transistor structure is electrically connected to the input or output, while the base is electrically connected to one of the two supply networks. The collector produces a current signal, which is used for triggering of the ESD protective element, when an ESD load occurs at the input or output.
Abstract:
Halbleiterbauelement (10), umfassend: – eine Source-Zone (16); – eine Drain-Zone (12); – eine Anordnung von Finnen (18), die zum Ermöglichen eines Stromflusses durch die Finnen (18) zwischen der Source-Zone (16) und der Drain-Zone (12) ausgebildet ist; – eine Gate-Zone (22), mit der die Finnen (18) operativ gekoppelt sind und die dazu ausgebildet ist, den Stromfluss durch die Finnen (18) zwischen der Source-Zone (16) und der Drain-Zone (12) zu steuern, und – mindestens ein Kühlelement (28; 30; 36; 40; 42; 44), das wenigstens zum Teil aus einem Material geformt ist, das eine Wärmekapazität hat, die gleich oder größer ist als die Wärmekapazität des Materials der Source-Zone, der Drain-Zone und der Anordnung von Finnen (18), wobei das Kühlelement (28; 30; 36; 40; 42; 44) sich in nächster Nähe zu und seitlich in dem Raum zwischen benachbarten Finnen (18) oder über den Finnen (18) befindet und von den Finnen (18), der Source-Zone (16) und der Drain-Zone (12) elektrisch isoliert ist.