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    METHOD FOR PRODUCING LOW-RESISTANCE OHMIC CONTACTS BETWEEN SUBSTRATES AND WELLS IN CMOS INTEGRATED CIRCUITS
    1.
    发明申请
    METHOD FOR PRODUCING LOW-RESISTANCE OHMIC CONTACTS BETWEEN SUBSTRATES AND WELLS IN CMOS INTEGRATED CIRCUITS 审中-公开
    在CMOS集成电路中生成基板和晶体管之间的低电阻OHMIC接触的方法

    公开(公告)号：WO2004032201A3

    公开(公告)日：2004-06-10

    申请号：PCT/EP0310218

    申请日：2003-09-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MAHNKOPF REINHARD ,  NEUMUELLER WALTER ,  PRIGGE ODIN ,  SCHAFBAUER THOMAS ,  SCHRUEFER KLAUS

    IPC: H01L21/266 ,  H01L21/74 ,  H01L21/8238

    CPC classification number: H01L21/743 ,  H01L21/266 ,  H01L21/74 ,  H01L21/823878 ,  H01L21/823892

    Abstract: A method of fabricating a semiconductor connective region of a first conductivity type through a semiconductor layer of a second conductivity type which at least partly separates a bulk portion of semiconductor body (substrate) of the first conductivity type from a semiconductor well of the first conductivity type includes a step of implanting ions into a portion of the layer to convert the conductivity of the implanted portion to the first conductivity type. This electrically connects the well to the bulk portion of the body. Any biasing potential applied to the bulk portion of the body is thus applied to the well. This eliminates any need to form a contact in the well for biasing the well and thus allows the well to be reduced in size.

    Abstract translation: 一种通过第二导电类型的半导体层制造第一导电类型的半导体连接区域的方法，该半导体层至少部分地将第一导电类型的半导体本体（衬底）的主体部分与第一导电类型的半导体阱分开 包括将离子注入该层的一部分以将注入部分的导电率转换为第一导电类型的步骤。 这将井与本体的主体部分电连接。 因此，施加到身体的主体部分的任何偏置电位被施加到井。 这消除了在井中形成用于偏压井的接触的任何需要，从而允许井的尺寸减小。

    METHOD TO PERFORM DEEP IMPLANTS WITHOUT SCATTERING TO ADJACENT AREAS
    2.
    发明申请
    METHOD TO PERFORM DEEP IMPLANTS WITHOUT SCATTERING TO ADJACENT AREAS 审中-公开
    在没有散射到相邻区域的情况下执行深部植入物的方法

    公开(公告)号：WO03105195A2

    公开(公告)日：2003-12-18

    申请号：PCT/EP0305934

    申请日：2003-06-05

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： SCHAFBAUER THOMAS ,  SPORTOUCH SANDRINE E

    IPC: H01L21/265 ,  H01L21/266 ,  H01L21/00

    CPC classification number: H01L21/2652 ,  H01L21/266

    Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening tocapture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

    Abstract translation: 一种通过在抗蚀剂掩模开口中施加散射离子捕获层以捕获散射在抗蚀剂中的任何注入的离子并从抗蚀剂偏转到掩模开口中以防止这些离子的方法，在具有深度注入的半导体衬底中和之上制造集成电路的方法 从而到达半导体衬底并影响掩模边缘处的离子浓度，从而影响集成电路的性能。

    7.
    发明专利
    未知

    公开(公告)号：DE59813748D1

    公开(公告)日：2006-11-16

    申请号：DE59813748

    申请日：1998-02-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERSCH ALFRED DR ,  SCHAFBAUER THOMAS

    IPC: G01K7/02 ,  H01L21/00 ,  G01K7/04 ,  H01L21/205 ,  H01L21/26 ,  H01L21/324

    Abstract: An apparatus for processing a substrate wafer wherein the apparatus includes a reaction chamber, a wafer holder intended to hold the substrate wafer, and a susceptor. A temperature sensor, preferably a thermocouple with two junctions, is provided for measuring the difference between the temperatures at the site of the susceptor and at a site between the susceptor and the substrate wafer.

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