公开(公告)号：DE10034897B4

公开(公告)日：2004-08-05

申请号：DE10034897

申请日：2000-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  POECHMUELLER PETER ,  SCHITTENHELM MICHAEL

IPC: G11C29/56 ,  G11C29/00 ,  G01R31/3183

Abstract: The address counter includes n programmable and/or fixed offset-registers (1-4) connected to selecting and logic circuits (5-8) for selecting the address offset values (a,b,c,d) stored in the offset registers and generating high frequency output addresses of the digital circuit under test. A control circuit receives m low-frequency input signals from the test equipment and generates n high frequency control signals for driving the selecting and logic circuits.

公开(公告)号：DE10141025A1

公开(公告)日：2003-03-13

申请号：DE10141025

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREBNER THOMAS ,  SCHITTENHELM MICHAEL ,  OSTENDORF HANS-CHRISTOPH ,  THALMANN ERWIN

IPC: G01R31/28 ,  G01R35/00 ,  H01L21/66

Abstract: A process for testing wafers in a test machine which can be calibrated automatically places a calibrating wafer (107) in the machine, calibrates it by means of a control unit and then inserts the wafer to be tested into the calibrated machine. An Independent claim is also included for a calibrating wafer for the above process.

公开(公告)号：DE10111440A1

公开(公告)日：2002-10-24

申请号：DE10111440

申请日：2001-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

IPC: G11C29/20 ,  G11C29/00

Abstract: The address generator has at least one base address register for temporarily storing a base address associated with an offset register group (13a..), first, second and third multiplexer circuits (38,17,25) and an addition circuit (60) that adds an address applied to a first input with a relative address applied to a second input to an address that is temporarily stored in the base address register.

公开(公告)号：DE10056882A1

公开(公告)日：2002-06-06

申请号：DE10056882

申请日：2000-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHITTENHELM MICHAEL

IPC: G01R31/14 ,  G01R35/00 ,  G01R31/28 ,  H01L21/66

公开(公告)号：DE10034854A1

公开(公告)日：2002-02-14

申请号：DE10034854

申请日：2000-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUEPKE JENS ,  ERNST WOLFGANG ,  KUHN JUSTUS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL ,  POECHMUELLER PETER ,  KRAUSE GUNNAR

IPC: G01R31/3183 ,  G11C29/10 ,  G11C29/00

Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

公开(公告)号：DE10034852A1

公开(公告)日：2002-02-07

申请号：DE10034852

申请日：2000-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  POECHMUELLER PETER ,  SCHITTENHELM MICHAEL

IPC: G11C29/50 ,  G11C29/56 ,  G11C29/00

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.