公开(公告)号：DE50100864D1

公开(公告)日：2003-12-04

申请号：DE50100864

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH DR ,  HEIN THOMAS ,  HEYNE PATRICK ,  MARKERT MICHAEL ,  MARX THILO ,  PARTSCH TORSTEN ,  SCHOENIGER SABINE ,  SCHROEGMEIER PETER ,  SOMMER MICHAEL ,  WEIS CHRISTIAN

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/133

Abstract: The circuit has input and output connections (1,2), first and second signal paths (3,4) with different delay times, a multiplexer (6), a drive circuit (5) with first and second programmable paths and transistors controled by complementary control signals and connected to nodes commonly connected to a multiplexer control input. Only one programmable path is programmed to be conducting and the other to be non-conducting.

公开(公告)号：DE10201431C1

公开(公告)日：2003-08-21

申请号：DE10201431

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  WEIS CHRISTIAN ,  ACHARYA PRAMOD

IPC: G11C29/40 ,  G01R31/3187 ,  G11C29/00 ,  H01L21/66

Abstract: An integrated circuit contains a register circuit for storing reference data for a test operation of the integrated circuit and a comparison circuit for comparing data to be read out. The comparison circuit outputs a plurality of comparison signals representing compressed comparison results. A plurality of output circuits are connected to the output of the comparison circuit, the output circuits receive one of the comparison signals in each case. The comparison signals are present at the output circuit over a plurality of clock edges or clock periods of a control clock. Each of the output circuits is connected to an interface pad for externally outputting the comparison signals. In the test operation, an external test device is connected to the interface pads of the integrated circuit. Despite a reduction in the transmission frequency to the test device, the full information content of the comparison signals can be transmitted.

公开(公告)号：DE10154066A1

公开(公告)日：2003-05-22

申请号：DE10154066

申请日：2001-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  HEIN THOMAS

IPC: G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10

Abstract: The memory has a cell field with row lines for cell selection, column lines for reading or writing data signals via read-write amplifiers and column selection lines for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads. A control circuit activates at least 2 different column selection lines with one column address and one of the column lines for 2 or more column addresses. The device has a memory cell field with row lines (WL1-4) for selecting cells and column lines for reading or writing data signals via read-write amplifiers (11,12,21,22) and column selection lines (CSL1,2) for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads (15,25). A control circuit activates at least two different column selection lines with one column address and one of the column lines for two or more column addresses. AN Independent claim is also included for the following: a method of operating an inventive device.

公开(公告)号：FR2822581A1

公开(公告)日：2002-09-27

申请号：FR0203604

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  SCHROGMEIER PETER ,  KIESER SABINE ,  WEIS CHRISTIAN

IPC: G11C11/417 ,  G06F13/40 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H04L25/49 ,  H03K19/00 ,  H04B1/69

Abstract: The method involves coding a data sequence by defining a current level and a voltage level for a data signal which is then transferred. The data signal is then decoded by evaluating the current and voltage levels to determine the data sequence transferred in data signal. An Independent claim is included for data transfer device.

公开(公告)号：GB2372841A

公开(公告)日：2002-09-04

申请号：GB0125220

申请日：2001-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: H02M3/07

Abstract: A voltage pump for generating an increased output voltage VPP has a turn-on control comprising a transistor 1 connected between a connection 3 for a supply voltage VEXT and a connection 4 for tapping-off the increased output voltage VPP. After the voltage pump 7 starts to operate, the increased output voltage VPP is decoupled from the supply voltage VEXT by the transistor 1. A switch 2 conveys the higher of the output voltage or supply voltage VPP, VEXT to the substrate connection and the gate connection of the transistor 1. The turn-on control makes possible an early provision of an increased output voltage with safe start-up operation of the voltage pump 7, only a small circuit complexity being necessary.

公开(公告)号：DE19929174C2

公开(公告)日：2001-09-27

申请号：DE19929174

申请日：1999-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

公开(公告)号：FR2822581B1

公开(公告)日：2006-05-12

申请号：FR0203604

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  SCHROGMEIER PETER ,  KIESER SABINE ,  WEIS CHRISTIAN

IPC: G11C7/10 ,  G11C11/417 ,  G06F13/40 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03M7/30 ,  H04B1/69 ,  H04L25/49

Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

公开(公告)号：DE19924244B4

公开(公告)日：2006-03-09

申请号：DE19924244

申请日：1999-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  SCHOENIGER SABINE ,  DIETRICH STEFAN ,  WEIS CHRISTIAN

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/24

Abstract: Each redundant unit of an integrated memory device is assigned respective programmable elements, comparison units, a code converting unit, a logic unit and a multiplexer. Each multiplexer has a first switching state, in which it connects outputs of the first comparison units to first inputs of the logic unit, and a second switching state, in which it connects outputs of the code converting unit to the first inputs of the logic unit. In the second switching state of the multiplexers, each redundant unit is assigned a different address in the unprogrammed state of the programmable elements. Therefore, redundant units can be selected individually for test purposes.

公开(公告)号：DE102004021694A1

公开(公告)日：2005-11-24

申请号：DE102004021694

申请日：2004-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  WEIS CHRISTIAN ,  SCHROEGMEIER PETER ,  HEIN THOMAS

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

Abstract: The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

公开(公告)号：DE102004015900A1

公开(公告)日：2005-10-27

申请号：DE102004015900

申请日：2004-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  WEIS CHRISTIAN ,  SCHROEGMEIER PETER

IPC: G06F13/10 ,  G06F13/42

Abstract: First (2) and second (3) semiconductor components (SC) fit in parallel to each other and can each be activated by first (CS0) and second (CS1) chip selection signals (CSS) so as to be controlled via a common control bus (6) and to use a common data bus (5). Assigned to the first SC, a first command decoder (10) decodes and operates commands (CMD) when the first CSS is activated. An independent claim is also included for a method for operating an integrated circuit for communicating data between multiple semiconductor components with a common data bus.