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公开(公告)号:BR9612189A
公开(公告)日:1999-07-13
申请号:BR9612189
申请日:1996-12-17
Applicant: INTEL CORP
Inventor: LIN DERRICK , VAKKALAGADDA RAMAMOHAN R , GLEW ANDREW F , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY
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公开(公告)号:BR9610285A
公开(公告)日:1999-03-16
申请号:BR9610285
申请日:1996-08-07
Applicant: INTEL CORP
Inventor: BINDAL AHMET , LIN DERRICK CHU , WITT WOLF , BUI TUAN H , KOWASHI EIICHI , FISHER STEPHEN A , DULONG CAROLE , MENNEMEIER LARRY M , MITTAL MILLIND , PELEG ALEXANDER D , EITAN BENNY
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公开(公告)号:MX9801571A
公开(公告)日:1998-05-31
申请号:MX9801571
申请日:1996-08-07
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , EITAN BENNY , MITTAL MILLIND , MENNEMEIER LARRY M , DULONG CAROLE , WITT WOLF , LIN DERRICK CHU , BINDAL AHMET , FISHER STEPHEN A
IPC: G06F7/53 , G06F5/00 , G06F7/00 , G06F7/48 , G06F7/483 , G06F7/49 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/57 , G06F9/302 , G06F9/305 , G06F9/38 , G06F15/78 , G06F17/14 , G06F17/16 , G06T1/20 , G06F07/00 , G06F07/52 , G06F15/76 , G06F15/80
Abstract: Un procesador, que tiene una primera y segunda áreas de almacenamiento con primeros y segundos datos empacados, respectivamente. Cada uno de los datos empacados incluye un primer, segundo, tercer y cuarto elemento de datos. Un circuito de multiplica-suma se acopla a la primera y segunda áreas de almacenamiento. El circuito de multiplica-suma incluye un primer (810), segundo (811), tercer (812) y cuarto (813) multiplicadores, en donde cada uno de los multiplicadores recibe un conjunto correspondiente de los elementos de datos. El circuito de multiplica-suma además un primer sumador (850) acoplado al primer y segundo multiplicadores (810, 811), y segundo sumador (851) acoplado al tercer y cuarto multiplicadores (812, 813). Una tercera área de almacenamiento (871) se acopla a los sumadores (850, 851). La tercer área de almacenamiento (871) incluye primer y segundo campos para guardar salida del primer y segundo sumadores (850, 851), respectivamente como primeros y segundos elementos de datos de terceros datos empacados.
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公开(公告)号:NO980873A
公开(公告)日:1998-04-28
申请号:NO980873
申请日:1998-02-27
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF , LIN CHU DERRICK , BINDAL AHMET
IPC: G06F7/53 , G06F5/00 , G06F7/00 , G06F7/48 , G06F7/483 , G06F7/49 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/57 , G06F9/302 , G06F9/305 , G06F9/38 , G06F15/78 , G06F17/14 , G06F17/16 , G06T1/20
CPC classification number: G06F7/5324 , G06F7/4812 , G06F7/49921 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F15/7857 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
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35.
公开(公告)号:AU1465497A
公开(公告)日:1997-07-28
申请号:AU1465497
申请日:1996-12-18
Applicant: INTEL CORP
Inventor: MENNEMEIER LARRY M , PELEG ALEXANDER D , MITTAL MILLIND , EITAN BENNY , DULONG CAROLE , KOWASHI EIICHI
Abstract: A computer system for processing multimedia data, wherein the data is transformed from a first domain to a second domain by performing two dimensional rotation on the data. The computer system includes a memory having stored therein a set of packed data sequences having data elements representing the digital data, and a sequence of instructions for transforming the digital data from a first domain to a second domain. The instructions, when executed, cause the processor to generate a first set of intermediate results in response to the execution of a first instruction which multiples data elements of a first packed data sequence with corresponding elements of a third packed data sequence, wherein the data elements of the third packed data sequence represent either a sine or cosine function. The instructions then cause the processor to generate a second set of intermediate results in response to the execution of a second instruction which multiplies the data elements of a second packed data sequence with corresponding data elements of a fourth packed data sequence, wherein the data elements of the fourth packed data sequence representing either a sine or cosine function. A set of first set of final results is generated in response to the execution of a third instruction which performs an arithmetic operation between corresponding data elements of the first and second sets of intermediate results. The final results represent the digital data transformed into the second domain.
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36.
公开(公告)号:ZA9610676B
公开(公告)日:1997-07-09
申请号:ZA9610676
申请日:1996-12-19
Applicant: INTEL CORP
Inventor: MENNEMEIER LARRY M , PELEG ALEXANDER D , DULONG CAROLE , KOWASHI EIICHI , MITTAL MILLIND , EITAN BENNY
Abstract: A computer system for processing multimedia data, wherein the data is transformed from a first domain to a second domain by performing two dimensional rotation on the data. The computer system includes a memory having stored therein a set of packed data sequences having data elements representing the digital data, and a sequence of instructions for transforming the digital data from a first domain to a second domain. The instructions, when executed, cause the processor to generate a first set of intermediate results in response to the execution of a first instruction which multiples data elements of a first packed data sequence with corresponding elements of a third packed data sequence, wherein the data elements of the third packed data sequence represent either a sine or cosine function. The instructions then cause the processor to generate a second set of intermediate results in response to the execution of a second instruction which multiplies the data elements of a second packed data sequence with corresponding data elements of a fourth packed data sequence, wherein the data elements of the fourth packed data sequence representing either a sine or cosine function. A set of first set of final results is generated in response to the execution of a third instruction which performs an arithmetic operation between corresponding data elements of the first and second sets of intermediate results. The final results represent the digital data transformed into the second domain.
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公开(公告)号:AU6677896A
公开(公告)日:1997-03-19
申请号:AU6677896
申请日:1996-07-17
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , YAARI YAACOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , GLEW ANDREW F , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF
IPC: G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78 , G06F7/00 , G06F7/38 , G06F7/52 , G06F7/50
Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.
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公开(公告)号:DE19681687B4
公开(公告)日:2008-04-03
申请号:DE19681687
申请日:1996-12-10
Applicant: INTEL CORP
Inventor: DULONG CAROLE , PELEG ALEXANDER D , MENNEMEIER LARRY M
Abstract: A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine including a transposition routine. The transposition routine manipulates data elements associated with the audio or video signal in transposing an array of n rows of a plurality of data elements. The transposition routine causes the processor to interleave data elements from a first row with data elements from a second row to generate a first result. Data elements from a third row are interleaved with data elements from a fourth row to generate a second result. Then, data elements from the first result are interleaved with data elements from the second result to generate a third result.\!
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公开(公告)号:AU722030B2
公开(公告)日:2000-07-20
申请号:AU1500497
申请日:1997-02-27
Applicant: INTEL CORP
Inventor: FISCHER STEPHEN , MENNEMEIER LARRY M , PELEG ALEXANDER D , DULONG CAROLE , KOWASHI EIICHI
Abstract: A method and apparatus for performing complex digital filters. According to one aspect of the invention, a computer system generally having a transmitting unit, a processor, and a storage device is described. The storage device is coupled to the processor and has stored therein a routine. When executed by the processor, the routine causes the processor to perform a digital filter on unfiltered data items using complex coefficients to generate an output data stream. Execution of the routine causes the processor to perform outer and inner loops. The outer loop steps through corresponding relationships between the complex coefficients and the unfiltered data items. Each of these corresponding relationships is used by the digital filter to generate the output data stream. The inner loop steps the complex coefficients. Within the inner loop, the unfiltered data item corresponding to the current complex coefficient is determined according to the current corresponding relationship. Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number. As a result of the manner in which these eight data elements are stored, the currently calculated complex number represents the product of the current complex coefficient and its corresponding unfiltered data item. The currently calculated complex number is then added to the current output packed data. As a result, the current output packed data stores the sum of the complex numbers generated in the current inner loop.
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公开(公告)号:AU717246B2
公开(公告)日:2000-03-23
申请号:AU6951196
申请日:1996-08-07
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF , LIN DERRICK CHU , BINDAL AHMET , BUI TUAN H , FISHER STEPHEN A
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