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公开(公告)号:AU2003223595A8
公开(公告)日:2003-11-03
申请号:AU2003223595
申请日:2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor: BASS DAVID S , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , LEVI ALAN M , DESAI BINISH , HEPLER EDWARD L , STARSINIC MICHAEL F
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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32.
公开(公告)号:AU2010200616B2
公开(公告)日:2013-08-22
申请号:AU2010200616
申请日:2010-02-19
Applicant: INTERDIGITAL TECH CORP
Inventor: MARINIER PAUL , CASTOR DOUGLAS R
Abstract: A method and apparatus for adjusting a channel quality indicator (CQI) feedback period to increase uplink capacity in a wireless communication system are disclosed. The uplink capacity is increased by reducing the uplink interference caused by CQI transmissions. A wireless transmit/received unit (WTRU) monitors a status of downlink transmissions to the WTRU and sets the CQl feedback period based on the status of the downlink transmissions to the WTRU. A base station monitors uplink and downlink transmission needs. The base station determines the CQI feedback period of at least one WTRU based on the uplink and downlink transmissions needs and sends a command to the WTRU to change the CQl feedback period of the WTRU. A WTfRU MONITORS A STATUS OF 102 DOWNLINK TRANSMiSSIONS TO THE WTRU. THE WTRU SETS THE CQt FEEDBACK PERIOD BASED ON THE STATUS OF DOWNUNK TRANSMISSIONS TO THE WTRU, (START 20 A BASE STATION MONITORS UPLINK TRANSMISSION NEEDS AND DOWNUNK TRANSMISSION NEEDS. Is fr 204 DESIRABLE TO CHANGE THE CQl FEEDBACK PERIOD OF AT LEAST ONE . NO WTRU BASED ON THE UPLINK TRANSMISSION NEEDS AND THE DOWNUINK TRANSMISSION NEEDS? THEBAE TAION SENDS A COMMAND TO THE WVTRUJ 206 TO CHANGE THE CQI FEEDBACK PERIOD OF THE WTRU.
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公开(公告)号:BRPI0616542A2
公开(公告)日:2011-06-21
申请号:BRPI0616542
申请日:2006-08-22
Applicant: INTERDIGITAL TECH CORP
Inventor: MARINIER PAUL , CASTOR DOUGLAS R
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34.
公开(公告)号:HK1120166A1
公开(公告)日:2009-03-20
申请号:HK08108825
申请日:2008-08-11
Applicant: INTERDIGITAL TECH CORP
Inventor: MARINIER PAUL , CASTOR DOUGLAS R
IPC: H04B17/40
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公开(公告)号:AR055390A1
公开(公告)日:2007-08-22
申请号:ARP060103678
申请日:2006-08-24
Applicant: INTERDIGITAL TECH CORP
Inventor: MARINIER PAUL , CASTOR DOUGLAS R
Abstract: Se divulga un método y aparato para ajustar el período de respuesta del indicador de calidad del canal (CQI) a los fines de aumentar la capacidad de enlace ascendente en un sistema de comunicacion inalámbrico. La capacidad de enlace ascendente se aumenta reduciendo la interferencia de enlace ascendente ocasionada por las transmisiones del CQI. Una unidad transmisora/receptora inalámbrica (WTRU) monitorea el estado de transmisiones de enlace descendente al WTRU y fija o establece el período de respuesta del CQI basado en el estado de las transmisiones de enlace descendente al WTRU. Una estacion base monitorea las necesidades de transmision de enlace ascendente y las de enlace descendente. La estacion base determina el período de respuesta del CQI de, por lo menos, un WTRU, basado en las necesidades de transmision de enlace ascendente y las de enlace descendente y envía una orden al WTRU a los fines de cambiar el período de respuesta del CQI del WTRU.
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公开(公告)号:NO20072807L
公开(公告)日:2007-07-26
申请号:NO20072807
申请日:2007-06-01
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , PIETRASKI PHILIP J , STERNBERG GREGORIO S
Abstract: A method and apparatus for adaptively biasing a channel quality indicator (CQI) used for setting a configuration of communication between a transmitter and a receiver in a wireless communication system. The receiver sends a CQI and positive acknowledgement (ACK)/negative acknowledgement (NACK) messages to the transmitter. The ACK/NACK messages indicate the absence or presence of error, respectively, in a transmitted data packet. The CQI is derived from the signal-to-interference ratio (SIR) and the ACK/NACK messages. The transmitter calculates the block error rate (BLER) of the transmitted data packets based upon the ACK/NACK messages sent from the receiver. The transmitter compares the BLER of the transmitted data packets to a target BLER and biases the CQI based on the comparison in order to achieve the target BLER.
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37.
公开(公告)号:AU2005274707A1
公开(公告)日:2006-02-23
申请号:AU2005274707
申请日:2005-07-19
Applicant: INTERDIGITAL TECH CORP
Inventor: DIFAZIO ROBERT A , ZEIRA ARIELA , REZNIK ALEXANDER , HACKETT WILLIAM C , HEPLER EDWARD L , KAEWELL JOHN DAVID JR , GAZDA ROBERT G , CASTOR DOUGLAS R
Abstract: A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals. The WTRU includes a modem host and a high speed downlink packet access (HSDPA) co-processor, which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.
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38.
公开(公告)号:CA2566263A1
公开(公告)日:2005-12-01
申请号:CA2566263
申请日:2005-05-03
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , LEVI ALAN M , DESAI BINISH P , MCCLELLAN GEORGE W
Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.
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39.
公开(公告)号:HK1065184A1
公开(公告)日:2005-02-08
申请号:HK04107103
申请日:2004-09-20
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , MCCLELLAN GEORGE W , MORABITO JOSEPH T
IPC: H03M13/23 , H03M13/27 , H03M13/29 , H04B1/69 , H04B7/155 , H04B7/208 , H04B7/212 , H04B7/216 , H04B7/26 , H04J3/00 , H04J3/02 , H04L1/00 , H04Q11/00 , H04W88/02 , H04W88/08
Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.
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公开(公告)号:AR033699A1
公开(公告)日:2004-01-07
申请号:ARP020101374
申请日:2002-04-16
Applicant: INTERDIGITAL TECH CORP
Inventor: MORABITO JOSEPH T , MCCLELLAN GEORGE W , CASTOR DOUGLAS R
IPC: H03M13/23 , H03M13/27 , H03M13/29 , H04B1/69 , H04B7/155 , H04B7/208 , H04B7/212 , H04B7/216 , H04B7/26 , H04J3/00 , H04J3/02 , H04L1/00 , H04Q11/00 , H04W88/02 , H04W88/08 , H04J13/00
Abstract: Formas de realización para ser utilizadas en el procesamiento de capas físicas. Una forma de realización determina el mapeo de direcciones de bits en el buffer de canales físicos desde la dirección de bits en el primer buffer intercalador. Las direcciones de buffer de canales físicos son determinadas con relación a las direcciones de los bits después de una adaptación de velocidad, aleatorización de bits, segundo intercalado y mapeo de canales físicos. Los bits son leídos directamente desde el primer buffer intercalador y son escritos en el buffer de canales físicos utilizando las direcciones de buffer de canales físicos determinadas. Otra forma de realización determina el mapeo de direcciones de bits en el primer buffer intercalador desde la dirección de bits en el buffer de canales físicos. Las primeras direcciones de buffer intercalador son determinadas con relación a direcciones de los bits después de una adaptación de velocidad inversa, aleatorización de bits inversa, segundo intercalado inverso y mapeo de canales físicos inverso. Los bits son leídos directamente desde las primeras direcciones de buffer intercalador y son escritos en las direcciones de buffer de canales físicos.
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