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31.发明专利
公开(公告)号：JP2005156888A
公开(公告)日：2005-06-16
申请号：JP2003394672
申请日：2003-11-25
Applicant: Matsushita Electric Works Ltd , 松下電工株式会社
Inventor： KONO KIYOHIKO , HARADA HIROSHI , OKA NAOMASA , NOGE HIROSHI , SUZUKI YUJI , OGIWARA ATSUSHI , JOMI HIROTAKA , USHIYAMA NAOKI
Abstract: PROBLEM TO BE SOLVED: To provide an optical fiber attitude detector and an optical fiber attitude detection method which enhance accuracy and work efficiency of positioning of an optical fiber.
SOLUTION: The optical fiber attitude detector is provided with: an illuminator 4 as a light projection means which irradiates the optical fiber 1b and a fixing member 2 with light from the side opposite from the fixing member 2 with the optical fiber 1b interposed between the illuminator and the fixing member; a camera 3 as an imaging means which images the optical fiber 1b and the fixing member 2 from the side opposite from the fixing member 2 with the optical fiber 1b interposed between the camera and and the fixing member; and a control part 6 which detects attitude of the optical fiber 1b based on light intensity distribution of a side of the optical fiber 1b obtained by performing image processing of an image of the camera 3. Thus, since it is not necessary to check the attitude of the optical fiber 1b by visual observation, the accuracy and the work efficiency of positioning of the optical fiber 1b are enhanced in comparison with the case of checking the attitude of the optical fiber 1b by the visual observation.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供一种提高光纤定位精度和工作效率的光纤姿态检测器和光纤姿态检测方法。 光纤姿态检测器设置有作为光投射装置的照明器4，其将光纤1b和固定部件2从与固定部件2相反的一侧照射光纤1b插入 在所述照明器和所述固定构件之间; 照相机3作为成像装置，其中光纤1b和固定构件之间插入光纤1b，使光纤1b和固定构件2从与固定构件2相反的一侧成像; 以及控制部6，其基于通过对照相机3的图像进行图像处理而获得的光纤1b的一侧的光强度分布来检测光纤1b的姿态。因此，由于不需要检查姿态 通过目视观察，光纤1b的定位精度和工作效率与通过视觉观察检查光纤1b的姿势的情况相比增强。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2003100588A
公开(公告)日：2003-04-04
申请号：JP2001288913
申请日：2001-09-21
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI , OKA NAOMASA , OKUTO TAKASHI
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for forming a resist film with a desired shape without generating resist residual on the surface of a substrate having a slanted face part. SOLUTION: A positive type resist formed on the surface of a substrate is exposed by using a first photo-mask for causing a light beam to be transmitted through a part corresponding to the shape of a resist coating film 21B to be formed. Then, the positive type resist is exposed by using a second photo- mask for causing a light beam to be transmitted through a slanted face part 11C and its outer boundary part 11E.
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33.发明专利
公开(公告)号：JP2003045872A
公开(公告)日：2003-02-14
申请号：JP2001226718
申请日：2001-07-26
Applicant: Matsushita Electric Works Ltd , 松下電工株式会社
Inventor： OKUTO TAKASHI , OKA NAOMASA , OGIWARA ATSUSHI
IPC: H01L21/3205 , H01L23/52
Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure in which incomplete wiring is eliminated without increasing the interval of adjacent lines at a part where the surface of a first semiconductor substrate abuts on the side face of a second semiconductor substrate.
SOLUTION: Wiring trenches 3 are formed on the surface 11 of a first semiconductor substrate 1 in correspondence with a specified wiring shape and a conductive path 4 is provided in the wiring trenches 3. A second semiconductor substrate 2 is bonded onto the surface 11 of the first semiconductor substrate 1 to cover a part of the conduction path 4.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供一种不增加在第一半导体衬底的表面与第二半导体衬底的侧面相邻的部分处的相邻线的间隔的消除不完全布线的布线结构。 解决方案：布线沟槽3形成在第一半导体衬底1的表面11上，与指定的布线形状相对应，并且在布线沟槽3中设置导电路径4.第二半导体衬底2结合到 第一半导体衬底1覆盖导电路径4的一部分。
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34.发明专利
公开(公告)号：JP2002015964A
公开(公告)日：2002-01-18
申请号：JP2000197731
申请日：2000-06-30
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OGIWARA ATSUSHI , OKA NAOMASA
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor wafer product for decoration use, capable of realizing variations of various colors, and to provide a manufacturing/sales system for the semiconductor wafer product which is advanced in cost reduction and in delivery-time shortening. SOLUTION: An electronic file of a drawing patter, which is desired by a customer, is transmitted from a terminal machine 7 of the customer to a printer 9 via a host computer 8 via a telecommunication circuit, and the drawing pattern is printed on an OHP sheet 10. The sheet is brought to a close contact with the surface of a semiconductor wafer 13 that has been covered by photoresist 12, and patterning takes place by irradiation it with a light 14. Namely, by using a commercially available inexpensive OHP film for the photomask, the semiconductor wafer product, on which a drawing pattern is drawn with the contrast among the semiconductor substrate can be manufactured and sold, insulating films and metal films at a low cost and a short delivery time, using conventional OA equipment.
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公开(公告)号：JPH11163020A
公开(公告)日：1999-06-18
申请号：JP32727697
申请日：1997-11-28
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： TANAKA YASUSHI , TAKAMI SHIGENARI , OKA NAOMASA , YASUIKE NORIYUKI , AWAI TAKAYOSHI , YOSHIDA HITOSHI , MOMOI YOSHINOBU , KUZUHARA KAZUNARI , INOUE TOMOHIRO
IPC: G01L1/18 , H01L21/60 , H01L21/822 , H01L27/04 , H01L29/84
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily detecting a stress on a semiconductor chip. SOLUTION: In a semiconductor device, a semiconductor chip 1 is mounted on a substrate 2. A strain detecting element 3 for detecting the strain in the semiconductor chip 1, and an electrode 4 for impressing an electric signal to the strain detecting element 3, and extracting an output from the strain detecting element 3 to the outside are formed at prescribed parts in the semiconductor chip 1. A measuring terminal 5 to be connected with the electrode 4 is formed in the substrate 2, and the measuring terminal 5 is connected with the electrode 4.
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Patent Agency Ranking
公开(公告)号：JPH10335586A
公开(公告)日：1998-12-18
申请号：JP14171197
申请日：1997-05-30
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OKA NAOMASA , KAMAKURA MASATOMO , OGIWARA ATSUSHI , OKUTO TAKASHI
IPC: H01L27/04 , H01L21/822
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device together with its manufacturing method, wherein a resistance value is adjusted with precision. SOLUTION: A thick silicon oxide film 2 is formed on a single crystal silicon substrate 1, and over it, a polysilicon layer 3a which, being of trapezoid where bottom side is longer, has such impurity distribution as an impurity concentration of phosphorus (P) becomes lower as going deeper under surface is formed. On the surface of polysilicon layer 3a, a silicon oxide film 4 is so formed that a film thickness is minimum near the interface between the polysilicon layer 3a and the silicon oxide film 2, while a polysilicon layer 3b comprising a not or phosphorous (P) is formed from over the silicon oxide film 4 on the polysilicon layer 3a across the silicon oxide film 2. Further, an inter-layer insulation film 5 is formed on such surface side of the single crystal silicon substrate 1 as the polysilicon layers 3a and 3b are formed, and the polysilicon layers 3a and 3b have a part of the silicon oxide film 4 and inter-layer insulation film 5 formed over them are removed, and connected electrically to aluminum wiring electrodes 6a and 6b, respectively.
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公开(公告)号：JPH08321477A
公开(公告)日：1996-12-03
申请号：JP12869095
申请日：1995-05-26
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OKA NAOMASA
IPC: H01L21/28 , H01L21/768 , H01L23/522
Abstract: PURPOSE: To prevent the breaking of wire by improving the coverage of a wiring metallic film within a contact hole. CONSTITUTION: A via hole 6 is made in a second interlayer insulating film by anisotropic etching, and an SOG film 5 is made on the insulating film 4 and on the inner face of the via hole 6. Then, the SOG film 5 is removed by wet etching. At this time, the SOG film 5 is etched from the top, so the overetching time becomes longer, the upper part of the second interlayer insulating film 4 it is, and the sectional form of the via hole 6 gets tapered. Next, the second wiring metallic film 7 consisting of aluminum is accumulated, whereupon it is made with favorable coverage.
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公开(公告)号：JPH02197136A
公开(公告)日：1990-08-03
申请号：JP1860289
申请日：1989-01-26
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OKA NAOMASA , SAIJO TAKASHI
IPC: H01L21/76 , H01L21/336 , H01L29/78
Abstract: PURPOSE:To facilitate a work and to improve the reverse withstand voltage characteristics of a device by a method wherein element formation regions are respectively covered with a mask provided with each sidewall on its side surfaces to inhibit the areas of the element formation regions from becoming narrow. CONSTITUTION:A thermal oxide film 2 is formed on the surface of a P-type Si substrate 1 and oxide films 2' only at element formation region parts are left by selective etching. Then, after a thermal oxide film 2'' is grown at a part, from which the film 2 is removed, an Si nitride film 3 is laminated. The film 3 is etched to form sidewalls (SWs) 13 consisting of an Si nitride film on the side surfaces of the films 2'. After boron is ion-implanted in surface parts 1a, field oxide films 5 and channel stopper regions 12 are formed by an oxidation treatment. The films 2' are removed by etching using a photoresist pattern to leave the SWs 13 and the element formation regions A are formed. MOSFETs are respectively formed at these regions A. Gate oxide films 8 are formed, gate electrodes 9 are respectively formed on them, phosphorus is ion- implanted using the electrodes 9 and the SWs 13 as masks to provide source and drain regions 10 and 11 and the SWs 13 are removed.
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公开(公告)号：JPH0260131A
公开(公告)日：1990-02-28
申请号：JP21298288
申请日：1988-08-26
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： OKA NAOMASA
IPC: H01L29/78 , H01L21/266 , H01L21/28 , H01L21/336
Abstract: PURPOSE:To improve the dimensional accuracy of the length of a channel even though the length of the channel is short by a method wherein sidewalls are used as marks in the feed of an impurity for the formation of an opposite conductivity type impurity region. CONSTITUTION:Sidewalls 14 are used as masks to cover a part which serves as a channel formation region. The accuracy of the lengths of the sidewalls 14 is affected by the respective fluctuations t and t' of the film thickness (t) of a thick oxide film 2' and the film thickness (t') of an Si nitride film 4 for sidewall formation use and a fluctuation in an etching (a side etching). In an etching process for the formation of the sidewalls 14, the sidewalls 14 are not etched at all their sides to come into contact to the side surfaces of the film 2' and the sides on the other side are etched only. Accordingly, the side etching affects one side only of the sidewalls. Therefore, an effect to the dimensional accuracy of a mask width, which is caused by a fluctuation in an etching treatment, is reduced by half.
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公开(公告)号：JPH01225349A
公开(公告)日：1989-09-08
申请号：JP5234888
申请日：1988-03-04
Applicant: MATSUSHITA ELECTRIC WORKS LTD
Inventor： KATO KAORU , OKA NAOMASA , SAKAMOTO SHINJI , HONDA YOSHIAKI , ARAKAWA MASAO
IPC: H01L21/762 , H01L21/76 , H01L27/00 , H01L29/78 , H01L29/786
Abstract: PURPOSE:To sharply increase an element formation area without increasing a size of an island region by forming a conductive layer at the outside of an insulating layer. CONSTITUTION:In a DI substrate 1, a conductive layer (polysilicon layer) 5 is arranged and installed at the outside of an insulating layer 3; an insulating layer (SiO2 layer) 6 used to electrically insulate this conductive layer 5 from a polysilicon layer 2 is formed between the conductive layer and the polysilicon layer; the insulating layer 3, an island-shaped region 4 and the conductive layer 5 are separated from the polysilicon layer 2 as a whole. The conductive layer 5 is formed in advance in a shape and with an area corresponding to an element to be formed in the island region 4. In the DI substrate 1, a V-groove is formed on the surface of an N silicon semiconductor wafer (not shown in the figure) by an anisotropic etching operation; the surface is thermally oxidized; an SiO2 layer for the insulating layer 3 is formed; a polysilicon layer for the conductive layer 5 is deposited on it to be thin; in addition, an SiO2 layer for the insulating layer 6 is formed. In succession, the polysilicon layer 2 is deposited to be thick; the wafer is polished from its outside until the bottom of the V-groove is exposed; then, the island region 4 is completed.
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