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    32.
    发明专利
    未知

    公开(公告)号：DE60308346D1

    公开(公告)日：2006-10-26

    申请号：DE60308346

    申请日：2003-07-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  PINNA CARLO

    IPC: H03M1/12 ,  G11C27/02

    Abstract: A boosted sampling circuit easy to realize, the input voltage of which may be greater than the maximum voltage level allowed by prior art circuits or even equal to the supply voltage, is disclosed.This result is attained by connecting the control nodes of the switches M2, M3 and M4 to the input node while the first control phase F1D is active, and by connecting a current terminal of the transistor M2 to a certain voltage for protecting it from breakdowns.A relative method of driving a boosted sampling circuit is also disclosed.

    33.
    发明专利
    未知

    公开(公告)号：IT1319613B1

    公开(公告)日：2003-10-20

    申请号：ITMI20002806

    申请日：2000-12-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PERNICI SERGIO ,  STEVENAZZI FABIO ,  NICOLLINI GERMANO

    IPC: G05F3/26 ,  G05F3/30

    Abstract: It is described a circuit generating a stable reference voltage with respect to temperature, which circuit is connected between first and second voltage references and comprises at least one current generating circuit adapted to inject a reference current into a resistive element connected between a base terminal of a bipolar transistor and an additional voltage reference. The bipolar transistor is connected between the first and second voltage references and to an output terminal of the generator circuit whereat the stable reference voltage with respect to temperature is. The generator circuit further comprises at least another resistive element, feedback connected between the output terminal of the generator circuit and the base terminal of the bipolar transistor to enable injecting additional current, having reverse dependence on temperature from the reference current, into the resistive element.

    35.
    发明专利
    未知

    公开(公告)号：DE69424668T2

    公开(公告)日：2001-01-25

    申请号：DE69424668

    申请日：1994-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

    IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07 ,  H02M3/00

    Abstract: An output voltage stabilisation circuit for a voltage multiplier of the type comprising a first charge transfer capacitor (C1) designed to take and transfer electrical charges from the input terminal (IN) to the output terminal (OUT) of a second capacitor (C2) for charge storage connected between the output terminal (OUT) and ground comprises an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage (Vrif) and the output voltage (Vout) of the voltage multiplier and said continuous voltage is applied to one terminal of said charge transfer capacitor (C1).

    36.
    发明专利
    未知

    公开(公告)号：DE69419897D1

    公开(公告)日：1999-09-09

    申请号：DE69419897

    申请日：1994-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  NAGARI ANGELO

    IPC: G11C27/02 ,  H03F3/00 ,  H03H19/00 ,  H03K5/24

    Abstract: A switched capacitor circuit (1) comprising an operational amplifier (OA), having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential, said operational amplifier (OA) being provided with a negative feedback network including a first capacitive element (C1) which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element (C2) which has a first terminal alternately connected to the second input terminal of the operational amplifier (OA) and to a reference potential, and a second terminal connected to a first circuit node (A) which is alternately connected to a signal input terminal (VIN) and said first output terminal (VOUT) of the operational amplifier (OA), the circuit (1) further comprising a third capacitive element (CX) connected between said circuit node (A) and a reference potential.

    37.
    发明专利
    未知

    公开(公告)号：DE69413814T2

    公开(公告)日：1999-02-25

    申请号：DE69413814

    申请日：1994-07-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

    Abstract: MOS-transistor switch without body effect comprising a pair of p-channel transistors (M1, M2) inserted in series between two connection terminals (A, B) and a third transistor (M3) with n-channel which is inserted between a connection node of the pair and a minimum potential reference (VSS) and a fourth transistor (M4) with n-channel in parallel with the pair of transistors (M1, M2). The substrates of the transistors of the pair are connected to the connection terminals (A, B). The substrate both of the third transistor (M3) and the fourth transistor (M4) is connected to the potential reference (VSS).

    40.
    发明专利
    未知

    公开(公告)号：DE69626021D1

    公开(公告)日：2003-03-06

    申请号：DE69626021

    申请日：1996-10-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  SENDEROWICZ DANIEL

    IPC: H03F3/45 ,  H03F1/00

    Abstract: The circuit of a two-stage fully differential amplifier composed of a differential input stage, two output stages and a common mode feedback circuit coupled to the output nodes of the amplifier includes a non-inverting stage coupled to a respective output node of the differential input stage for driving the respective output stage. Each auxiliary non-inverting stage of the two branches of the fully differential amplifier uses as a biasing current generator, the load device of the branch of the differential input stage to the output of which the non-inverting stage is coupled. The modified circuit of the fully differential amplifier permits the use of a null-consumption common mode feedback circuit as normally employed in a single stage fully differential amplifier.

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