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    31.
    发明专利
    未知

    公开(公告)号：DE69841104D1

    公开(公告)日：2009-10-08

    申请号：DE69841104

    申请日：1998-12-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARLOCCHI GABRIELE ,  VILLA FLAVIO

    IPC: H01L21/301 ,  H01L21/762 ,  H01L27/12

    Abstract: The method comprises the steps of: on a wafer (1) of monocrystalline semiconductor material, forming a hard mask (9) of an oxidation-resistant material, defining first protective regions (7) covering first portions (21) of the wafer (1); excavating the second portions (8'') of the wafer (1), forming initial trenches (10) extending between the first portions (8') of the wafer (1); thermally oxidating the wafer (1), forming a sacrificial oxide layer (14) extending at the lateral and base walls (10a, 10b) of the initial trenches (10), below the first protective regions (7); and wet etching the wafer (1), to completely remove the sacrificial oxide layer (14). Thereby, intermediate trenches (10') are formed, the lateral walls (10a') of which are recessed with respect to the first protective regions (7). Subsequently, a second oxide layer 11 is formed inside the intermediate trenches 10'; a second silicon nitride layer 12 is deposited; final trenches 16 are produced; a buried oxide region 22 is formed, and finally an epitaxial layer 23 is grown.

    32.
    发明专利
    未知

    公开(公告)号：DE69935495D1

    公开(公告)日：2007-04-26

    申请号：DE69935495

    申请日：1999-04-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARLOCCHI GABRIELE ,  VILLA FLAVIO ,  CORONA PIETRO

    IPC: H01L21/764 ,  B01L3/00 ,  B81C1/00 ,  H01L21/20

    Abstract: The process comprises the steps of forming, on a monocrystalline-silicon body (11), an etching-aid region (13) of polycrystalline silicon; forming, on the etching-aid region (13), a nucleus region (17) of polycrystalline silicon, surrounded by a protective structure (26) having an opening (22') extending as far as the etching-aid region (13); TMAH-etching the etching-aid region (13) and the monocrystalline body (11), forming a tub shaped cavity (30); removing the top layer (19) of the protective structure (26); and growing an epitaxial layer (33) on the monocrystalline body (11) and the nucleus region (17). The epitaxial layer, of monocrystalline type (33a) on the monocrystalline body (11) and of polycrystalline type (33b) on the nucleus region (17), closes upwardly the etching opening (22'), and the cavity (30) is thus completely embedded in the resulting wafer (34).

    35.
    发明专利
    未知

    公开(公告)号：DE69627645D1

    公开(公告)日：2003-05-28

    申请号：DE69627645

    申请日：1996-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIGNA BENEDETTO ,  FERRARI PAOLO ,  VILLA FLAVIO

    IPC: G01L9/06 ,  B81B3/00 ,  B81C1/00 ,  G01L9/00 ,  H01L29/84

    Abstract: The pressure sensor is integrated in a SOI (Silicon-on-Insulator) substrate using the insulating layer as a sacrificial layer, which is partly removed by chemical etching to form the diaphragm. To fabricate the sensor, after forming the piezoresistive elements (10) and the electronic components (4, 6-8) integrated in the same chip, trenches (26) are formed in the upper wafer (23) of the substrate and extending from the surface to the layer of insulating material (22); the layer of insulating material (22) is chemically etched through the trenches (26) to form an opening (31) beneath the diaphragm (27); and a dielectric layer (25) is deposited to outwardly close the trenches (26) and the opening (31). Thus, the process is greatly simplified, and numerous packaging problems eliminated.

    37.
    发明专利
    未知

    公开(公告)号：DE69428407T2

    公开(公告)日：2002-05-29

    申请号：DE69428407

    申请日：1994-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA FLAVIO

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/73 ,  H01L29/36

    Abstract: A low-noise transistor comprising a cutoff region (38; 47) laterally surrounding the emitter region (36; 45) in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. In the NPN transistor, the cutoff region is formed by a P ring (38) in a P type well region (35), and, in the PNP transistor, by the N type enriched base region (47) between the emitter region (45) and the collector region (49).

    38.
    发明专利
    未知

    公开(公告)号：DE69428407D1

    公开(公告)日：2001-10-31

    申请号：DE69428407

    申请日：1994-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA FLAVIO

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/73 ,  H01L29/36

    Abstract: A low-noise transistor comprising a cutoff region (38; 47) laterally surrounding the emitter region (36; 45) in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. In the NPN transistor, the cutoff region is formed by a P ring (38) in a P type well region (35), and, in the PNP transistor, by the N type enriched base region (47) between the emitter region (45) and the collector region (49).

    39.
    发明专利
    未知

    公开(公告)号：DE69326340T2

    公开(公告)日：2000-01-13

    申请号：DE69326340

    申请日：1993-09-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA FLAVIO

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735

    Abstract: A low-noise transistor comprising a cutoff region (38; 47) laterally surrounding the emitter region (36; 45) in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. In the NPN transistor, the cutoff region is formed by a P ring (38) in a P type well region (35), and, in the PNP transistor, by the N type enriched base region (47) between the emitter region (45) and the collector region (49).

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