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    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
    33.
    发明公开
    Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit 审中-公开
    从交错突发存储器和相应的电路的控制协议的地址释放信号（ALE）的内部再生

    公开(公告)号：EP1122733A1

    公开(公告)日：2001-08-08

    申请号：EP00200752.4

    申请日：2000-03-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicosia, Salvatore ,  Tomaiuolo, Francesco ,  Campanale, Fabrizio ,  De Ambroggi, Luca Giuseppe ,  Pascucci, Luigi

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

    Abstract: An interleaved memory readable in sequential access synchronous mode and in random access asynchronous mode, in function of external protocol signals ( ALE; CEn, RD ), has a circuit of internal regeneration of an external input address latch enabling signal ( ALE ), filtered by a second external chip enable signal ( CEn ). The circuit comprises a latch ( LATCH ) storing the external signal ( ALE_EXT ) of input address latch enabling and a NOR gate combining the output ( ALE_BUFF ) of the latch with the second external signal of chip enable ( CEn ) and producing a first internal replica signal of address latch enabling ( ALE_FAST ). Delay circuits in cascade to the output of the latch and in cascade of the input pad of the external signal of chip enable ( CEn ) and logic means combining the internally generated replica signal ( ALE_FAST ) and the signal ( ALE_BUFF ) present at the output of the latch with signals retarded by said delay circuits produce set and reset signals of an output flip-flop outputting a second internally generated reconditioned address latch enabling signal ( ALE ). The reconditioned signal has a raising edge conditionally retarded compared to the raising edge of the external command ( ALE_EXT ) and a duration that is conditionally incremented such to compensate for eventual critical asynchronisms between the two protocol external signals ( ALE_EXT, CEn ) in the different modes of operation of the interleaved memory.

    Abstract translation: 一种交错的存储器可读在顺序访问同步模式和在随机存取异步模式下，在外部协议信号的功能（ALE; CEN，RD）具有外部输入地址锁存器的内部再生的电路启动信号（ALE），通过过滤 第二外部芯片使能信号（CEN）。 该电路包括一个锁存器（LATCH）存储输入地址锁存器的外部信号（ALE_EXT）启用和NOR门的锁存器的输出（ALE_BUFF）相结合的芯片使能（CEN）的第二外部信号，并产生第一内部复制品 地址的信号锁存启用（ALE_FAST）。 在级联延迟电路的锁存器的输出和在芯片的外部信号的输入焊盘的级联使能（CEN）和逻辑装置组合所述内部生成的复制信号（ALE_FAST）和信号（ALE_BUFF）存在的输出 与由所述延迟电路延迟的锁存信号产生置位和复位的输出触发器输出婷第二内部产生的修复地址锁存使能信号（ALE）的信号。 该翻新信号具有上升沿有条件延迟相比于外部命令（ALE_EXT）的上升沿和一个持续时间没有条件指针累加寻求以补偿不同的模式这两种协议的外部信号（ALE_EXT，CEN）之间最终临界异步性 的交错存储器的操作。

    Circuit and method for reading a non-volatile memory
    37.
    发明公开
    Circuit and method for reading a non-volatile memory 失效
    Schaltung und Verfahren zum Lesen einesnichtflüchtigenSpeichers

    公开(公告)号：EP0974976A1

    公开(公告)日：2000-01-26

    申请号：EP98830438.2

    申请日：1998-07-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi

    IPC: G11C7/00 ,  G11C16/06

    CPC classification number: G11C7/1021 ,  G11C16/28

    Abstract: A method for reading a non-volatile memory, comprising the steps of:

    -- providing a first random memory reading cycle;
    -- performing, at the end of the random reading cycle, a collective page precharge;
    -- subsequently performing a reading cycle of the page or random type, depending on whether the subsequent reading must be performed within the same page or not; and
    if a page reading cycle is performed, executing, when the data item is captured, a page precharge step in preparation both for page reading and for random reading.

    Abstract translation: 一种用于读取非易失性存储器的方法，包括以下步骤：提供第一随机存储器读取周期; 在随机阅读周期结束时执行集体页面预充电; 随后执行页面或随机类型的读取周期，这取决于后续读取是否必须在同一页面内执行; 并且如果执行了页面读取周期，则当捕获数据项时执行页面预充电步骤，以准备页面读取和随机读取。

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