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    Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof
    31.
    发明公开
    Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof 有权
    次光刻接触结构，特别是用于相变存储器元件，和它们的制备方法

    公开(公告)号：EP1439583A1

    公开(公告)日：2004-07-21

    申请号：EP03425016.7

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama, ,  Pollaccia, Giorgio ,  Pellizzer, Fabio

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

    Abstract: A contact structure (98) for a PCM device is formed by an elongated formation (102) having a longitudinal extension parallel to the upper surface (92) of the body (91) and an end face (110) extending in a vertical plane. The end face (110) is in contact with a bottom portion of an active region (103) of chalcogenic material so that the dimensions of the contact area defined by the end face (110) are determined by the thickness (S) of the elongated formation and by the width (W) thereof.

    Abstract translation: 用于PCM器件的接触结构（98）通过在细长结构（102）具有平行于所述主体（91）和在端面（110）的上表面（92）的纵向延伸在一个垂直平面延伸而形成。 端面（110）与硫族化物材料的有源区（103）的底部部分，从而没有通过所述端面（110）中定义的接触区域的尺寸是确定的由细长的厚度（S）开采的接触 形成和由所述宽度（W）上。

    Phase change memory cell and manufacturing method thereof using minitrenches
    32.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    Phasenwechsel-Speicherzelle sowie deren Herstellungsverfahren手套Minigräben

    公开(公告)号：EP1339110A1

    公开(公告)日：2003-08-27

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一尺寸的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一薄部分（22）和第二薄部分（38a）直接电接触并限定亚光刻延伸部分的接触区域（58）。 第二薄部分（38a）由限定光刻开口（51）的模制层（49）围绕的氧化物间隔部分（55a）横向限定。 间隔物部分（55a）通过间隔物形成技术在形成光刻开口之后形成。

    Transistor structure with high input impedance and high current capability and manufacturing process thereof
    36.
    发明公开
    Transistor structure with high input impedance and high current capability and manufacturing process thereof 有权
    晶体管结构具有高输入阻抗，高电流容量及其生产方法

    公开(公告)号：EP1791181A1

    公开(公告)日：2007-05-30

    申请号：EP05425835.5

    申请日：2005-11-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Cappelletti, Paolo Giuseppe

    IPC: H01L27/07 ,  H01L21/8249 ,  H01L27/24

    CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/0705

    Abstract: Integrated transistor device (10) formed in a chip of semiconductor material (15) having an electrical-insulation region (31) delimiting an active area (30) accommodating a bipolar transistor (11) of vertical type and a MOSFET (12) of planar type, contiguous to one another. The active area accommodates a collector region (18); a bipolar base region (19) contiguous to the collector region; an emitter region (20) within the bipolar base region; a source region (23), arranged at a distance from the bipolar base region; a drain region (24); a channel region (22) arranged between the source region and the drain region; and a well region (35). The drain region (24) and the bipolar base region (19) are contiguous and form a common base structure (19, 24, 37) shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device (10) has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

    Abstract translation: 在具有电绝缘区（31），在有源区（30）限定容纳垂直型的平面的一个双极型晶体管（11）和一个MOSFET（12）的半导体材料的芯片（15）上综合晶体管装置（10） 型，邻接彼此。 有源区可容纳的集电极区域（18）; 双极基极区域（19）邻接所述集电极区; 到发射极双极基极区域内的区域（20）; 一个源极区（23），在从双极基极区域的距离布置; 漏极区（24）; 源区和漏区之间设置的沟道区（22）; 和一个阱区（35）。 漏极区（24）和双极基极区域（19）是连续的，并形成由双极晶体管和MOSFET共有的共有底边结构（19，24，37）。 由此，集成晶体管装置（10）具有高输入阻抗和能够驱动大电流，同时仅需要一个小的积分区。

    A content addressable memory cell
    39.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP1526547A1

    公开(公告)日：2005-04-27

    申请号：EP03103898.7

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    40.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件，特别是相变存储器，具有硅化方法

    公开(公告)号：EP1439579A1

    公开(公告)日：2004-07-21

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Abstract translation: 的方法worin到绝缘区域（13）在一个主体中形成至少围绕到一半导体主体的阵列部分（51）（10）; 半导体材料的栅极区（16）形成在所述半导体主体的一个电路部分（51）的顶部（10）; 的第一硅化物保护掩模（52）是形成在阵列部分的顶部上; 栅极区（16）和所述电路部（51）的有源区（43）被硅化并且所述第一硅化物保护掩模（52）被去除。 第一硅化物保护掩模（52）是多晶硅，并且与所述栅极区域（16）同时形成。 覆盖所述第一硅化物保护掩模（52）的介电材料的第二硅化物保护掩模（53）的栅极区（16）的硅化之前形成。 第二硅化物保护掩模（53）与形成尾盘反弹到栅极区域（16）间隔件（41）同时形成。

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