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    32.
    发明专利
    未知

    公开(公告)号：DE19734837B4

    公开(公告)日：2004-04-15

    申请号：DE19734837

    申请日：1997-08-12

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

    Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

    Forming capacitor electrodes for integrated circuits
    34.
    发明专利
    Forming capacitor electrodes for integrated circuits 未知

    公开(公告)号：GB2333178A

    公开(公告)日：1999-07-14

    申请号：GB9800587

    申请日：1998-01-12

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI ,  SHIH HSUE-HAO

    IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

    Abstract: In a method for fabricating a hemispherical grain silicon structure as a bottom electrode of a capacitor in an integrated circuit, poly-silicon is formed as the seed for nucleation instead of amorphous silicon. A silicon oxide layer 24 provided with a contact hole 22 is formed on a substrate 20. The contact hole is filled with polysilicon and patterned to form a capacitor electrode 26. Native oxide on the electrode is removed by H 2 or HCI solution and then, using chlorosilane as a precursor, a hemispherical grain silicon structure 28 is grown on the electrode by CVD to increase its capacitance. The by-products H 2 and HCI of the reaction prevent growth of the structure 28 on the silicon oxide layer 24.

    Multilevel interconnect structure for high density integrated circuit devices, integrated circuit memories
    35.
    发明专利
    Multilevel interconnect structure for high density integrated circuit devices, integrated circuit memories 未知

    公开(公告)号：NL1007464C2

    公开(公告)日：1999-05-07

    申请号：NL1007464

    申请日：1997-11-06

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/768 ,  H01L21/033

    Abstract: A multilevel interconnect is formed which uses air (74) as a dielectric between wiring lines (66) bounded on an upper surface by a capping layer (70). A sacrificial layer is used to separate the wiring lines and is consumed leaving air gaps. A multilevel interconnect is formed which uses air as a dielectric between wiring lines. A pattern of wiring lines is formed over an insulating layer (62), a first wiring line is laterally separated from a second wiring line by a sacrificial layer. The surface of this layer is recessed below the surfaces of the wiring lines. A capping layer (70) is formed over the recessed surface and the wiring lines. The sacrificial layer is consumed through the capping layer leaving an air dielectric (74) between the two wiring lines bounded on an upper surface by the capping layer.

    Forming capacitors, e.g. for DRAMs
    36.
    发明专利
    Forming capacitors, e.g. for DRAMs 未知

    公开(公告)号：GB2330691A

    公开(公告)日：1999-04-28

    申请号：GB9722664

    申请日：1997-10-27

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

    Abstract: A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region 22 of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon 36 deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer (38) is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon 40 is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide (38) is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon 36. A second layer of polysilicon 44 is deposited over the remaining grains of hemispherical grained polysilicon and over the column-shaped portions of the oxide layer 42 left by the etching stop. A capacitor dielectric 46 is formed over the second layer of polysilicon and then an upper capacitor electrode 50 is provided.

    39.
    发明专利
    未知

    公开(公告)号：NL1006872C2

    公开(公告)日：1999-03-02

    申请号：NL1006872

    申请日：1997-08-28

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/266

    Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

    Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI
    40.
    发明专利
    Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI 未知

    公开(公告)号：NL1006803C2

    公开(公告)日：1999-02-23

    申请号：NL1006803

    申请日：1997-08-20

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI ,  TSAI MENG-JIN

    IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/316 ,  H01L21/8234

    Abstract: Production if an IC device requires the following steps to be performed - Provide semiconductor substrate with surface and that substrate has a 1st area, which will generate 1st MOS devices and a 2nd area which will generate several 2nd MOS devices; - Provide 1st dopant of 1st density on 1st area surface of substrate; - Provide 2nd dopant of 2nd density on 2nd area surface of substrate; - Oxidation substrate surface in single oxidation process, and generate oxide with 1st thickness on 1st area, and generate oxide with 2nd different thickness on 2nd area of substrate; - Generate 1st MOS device with 1st thickness oxide on 1st area, and generate 2nd MOS device with 2nd thickness oxide on 2nd area of substrate.

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