公开(公告)号：US11943877B2

公开(公告)日：2024-03-26

申请号：US17684421

申请日：2022-03-02

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

IPC: H05K3/24 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/488 ,  H01L23/544 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

公开(公告)号：US20230137841A1

公开(公告)日：2023-05-04

申请号：US18089465

申请日：2022-12-27

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Ra-Min Tain ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng ,  Chun-Hsien Chien

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

Abstract: A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

公开(公告)号：US20220336333A1

公开(公告)日：2022-10-20

申请号：US17233551

申请日：2021-04-19

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Chi-Hai Kuo ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

公开(公告)号：US20220246810A1

公开(公告)日：2022-08-04

申请号：US17209110

申请日：2021-03-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang

IPC: H01L33/62 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L33/54

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

公开(公告)号：US20220208630A1

公开(公告)日：2022-06-30

申请号：US17155094

申请日：2021-01-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Pei-Chi Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

公开(公告)号：US10854803B2

公开(公告)日：2020-12-01

申请号：US16842716

申请日：2020-04-07

Applicant: Unimicron Technology Corp.

Inventor： Pei-Wei Wang ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  De-Shiang Liu ,  Tzyy-Jang Tseng

IPC: H01L33/62

Abstract: A manufacturing method of a light emitting device package structure is provided. The method includes following operations: (i) providing a circuit redistribution structure; (ii) providing a first substrate; (iii) forming a circuit layer structure over the first substrate, wherein the circuit layer structure includes a first circuit layer; (iv) before or after operation (iii), placing a light emitting device between the first substrate and the circuit layer structure or over the circuit layer structure, wherein the light emitting device is electrically connected with the first circuit layer; and (v) placing the circuit redistribution structure over the light emitting device, wherein the circuit redistribution structure includes a first redistribution layer, a second redistribution layer, and a chip, and the first redistribution layer includes a second circuit layer and a conductive contact that contacts the second circuit layer.

公开(公告)号：US10651358B2

公开(公告)日：2020-05-12

申请号：US16140563

申请日：2018-09-25

Applicant: Unimicron Technology Corp.

Inventor： Pei-Wei Wang ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  De-Shiang Liu ,  Tzyy-Jang Tseng

IPC: H01L33/62

Abstract: A light emitting device package structure includes a substrate, a circuit layer structure, a light emitting device, a first redistribution layer, a conductive connector, a second redistribution layer, and a chip. The circuit layer structure is disposed over the substrate, and the circuit layer structure includes a first circuit layer. The light emitting device is disposed over the circuit layer structure and is electrically connected with the first circuit layer. The first redistribution layer is disposed over the light emitting device and includes a second circuit layer and a conductive contact contacting the second circuit layer. The conductive connector connects the first circuit layer and the second circuit layer. The second redistribution layer is disposed over the first redistribution layer and includes a third circuit layer contacting the conductive contact. The chip is disposed over the second redistribution layer and is electrically connected with the third circuit layer.

公开(公告)号：US10588214B2

公开(公告)日：2020-03-10

申请号：US16543609

申请日：2019-08-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen

IPC: H05K1/02 ,  H05K1/11

Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.

公开(公告)号：US20200043890A1

公开(公告)日：2020-02-06

申请号：US16152424

申请日：2018-10-05

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package structure is also provided.

公开(公告)号：US20180070452A1

公开(公告)日：2018-03-08

申请号：US15256757

申请日：2016-09-06

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  H05K3/24 ,  G03F7/16 ,  G03F7/20 ,  G03F7/09 ,  G03F7/32 ,  G03F7/40 ,  G03F1/50 ,  G03F1/76

CPC classification number: G03F1/50 ,  G01K7/24 ,  G01K15/007 ,  G03F7/2032 ,  G03F7/2047 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/107 ,  H05K3/1275 ,  H05K3/182 ,  H05K3/241 ,  H05K3/422

Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.