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    Process for filling etched holes
    32.
    发明授权
    Process for filling etched holes 有权

    公开(公告)号：US09708183B2

    公开(公告)日：2017-07-18

    申请号：US15046239

    申请日：2016-02-17

    Applicant: Memjet Technology Ltd.

    Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC: B81C1/00 ,  B41J2/16

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    PROCESS FOR FILLING ETCHED HOLES
    33.
    发明申请
    PROCESS FOR FILLING ETCHED HOLES 有权
    填充蚀刻孔的方法

    公开(公告)号：US20160236930A1

    公开(公告)日：2016-08-18

    申请号：US15046239

    申请日：2016-02-17

    Applicant: Memjet Technology Ltd.

    Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC: B81C1/00

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    Abstract translation: 一种用于填充限定在晶片衬底的前表面中的一个或多个蚀刻孔的工艺。 该方法包括以下步骤：（i）将热塑性第一聚合物层沉积到前表面和每个孔中; （ii）回流第一聚合物; （iii）将晶片衬底暴露于受控氧化等离子体; （iv）任选地重复步骤（i）至（iii）; （v）沉积可光成像的第二聚合物层; （vi）使用曝光和显影从所述孔的外周边区域选择性地除去所述第二聚合物; 和（vii）平面化前侧表面以提供填充有彼此不同的第一和第二聚合物的塞子的孔。 每个插头具有与前侧表面共面的相应的上表面。

    Process for Reconditioning Semiconductor Surface to Facilitate Bonding
    34.
    发明申请
    Process for Reconditioning Semiconductor Surface to Facilitate Bonding 有权
    修复半导体表面以促进粘合的工艺

    公开(公告)号：US20120295371A1

    公开(公告)日：2012-11-22

    申请号：US13574347

    申请日：2011-01-26

    Applicant: Parthiban Arunasalam

    Inventor： Parthiban Arunasalam

    IPC: H01L21/306

    CPC classification number: H01L21/302 ,  B81C1/00611 ,  B81C2201/0121 ,  B81C2203/036 ,  H01L21/02057

    Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.

    Abstract translation: 用于促进在接合界面表面具有微观结构缺陷的诸如硅晶片的半导体部件的接合的非研磨方法。 在优选的方法中，通过在接合界面上形成氧化层到低于缺陷水平的深度除去微结构缺陷，然后除去氧化物层以暴露出令人满意的粘结表面，从而提高生产线产量并降低 制造设施中的废料触发。

    Microelectromechanical device having a common ground plane layer and a set of contact teeth and method for making aspects thereof
    35.
    发明授权
    Microelectromechanical device having a common ground plane layer and a set of contact teeth and method for making aspects thereof 有权
    具有公共接地层和一组接触齿的微机电装置及其制造方法

    公开(公告)号：US07545234B2

    公开(公告)日：2009-06-09

    申请号：US11332715

    申请日：2006-01-13

    Applicant: Chia-Shing Chou

    Inventor： Chia-Shing Chou

    IPC: H01H51/22

    CPC classification number: B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

    Abstract: The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer.

    Abstract translation: 本发明涉及MEM开关。 更具体地，本发明涉及一种用于制造具有公共接地层的MEM开关的系统和方法。 制造MEM开关的一种方法包括：在衬底上构图公共接地层; 在公共接地层上形成介电层; 通过所述电介质层沉积DC电极区域以接触所述公共接地层; 以及在所述直流电极区域上沉积导电层，使得所述导电层的区域接触所述直流电极区域，使得所述公共接地层提供所述导电层的区域的公共接地。

    Method for producing optically planar surfaces for micro-electromechanical system devices
    36.
    发明授权
    Method for producing optically planar surfaces for micro-electromechanical system devices 有权
    微机电系统装置的光学平面的制造方法

    公开(公告)号：US06426237B2

    公开(公告)日：2002-07-30

    申请号：US09867928

    申请日：2001-05-30

    Applicant: Joseph Jech, Jr. ,  John A. Lebens ,  John C. Brazas, Jr. ,  Marek W. Kowarz

    Inventor： Joseph Jech, Jr. ,  John A. Lebens ,  John C. Brazas, Jr. ,  Marek W. Kowarz

    IPC: H01L21302

    CPC classification number: B81C1/00611 ,  B81C2201/0121

    Abstract: A method for producing optically planar surfaces for micro-electromechanical system devices (MEMS), comprising the steps of: depositing a first layer over a substrate; forming a channel in the first layer wherein the channel has a depth defined by a thickness of the first layer and a width greater than 10 microns; depositing a second layer over the first layer wherein the second layer has a thickness greater than the depth of the channel and is composed of a different material than the first layer; removing the second layer from outside the channel leaving an overlap at the edge of the channel; and polishing the second layer that fills the channel to obtain an optically planar surface for the MEMS device.

    Abstract translation: 一种用于制造用于微机电系统装置（MEMS）的光学平面的方法，包括以下步骤：在衬底上沉积第一层; 在第一层中形成通道，其中通道具有由第一层的厚度和大于10微米的宽度限定的深度; 在所述第一层上沉积第二层，其中所述第二层的厚度大于所述沟道的深度，并且由与所述第一层不同的材料构成; 从所述通道外部移除所述第二层，在所述通道的边缘处留下重叠; 并抛光填充通道的第二层以获得用于MEMS器件的光学平面表面。

    MEMS DEVICE HAVING CONDUCTIVE MICROSTRUCTURES LATERALLY SURROUNDED BY OXIDE MATERIAL
    40.
    发明申请
    MEMS DEVICE HAVING CONDUCTIVE MICROSTRUCTURES LATERALLY SURROUNDED BY OXIDE MATERIAL 审中-公开
    具有导电性微结构的MEMS器件由氧化物材料

    公开(公告)号：US20150291414A1

    公开(公告)日：2015-10-15

    申请号：US14688546

    申请日：2015-04-16

    Applicant: Freescale Semiconductor, Inc.

    Inventor： LIANJUN LIU

    IPC: B81B3/00

    CPC classification number: B81B3/0021 ,  B81B2207/096 ,  B81C1/00134 ,  B81C1/00611 ,  B81C2201/0121 ,  B81C2203/00

    Abstract: A MEMS device includes a first substrate structure and a second substrate structure. The first substrate structure has a conductive microstructure and an oxide material surrounding lateral side of the conductive microstructure. A thickness of the conductive microstructure and a thickness of the oxide material are approximately equivalent. The second substrate structure has an active region of the MEMS device, and the second substrate structure is coupled in spaced apart relationship with the first substrate structure to produce a cavity between the structures. The active region of the MEMS device is suspended above the cavity and the conductive microstructure underlies the cavity. The conductive microstructure is formed from a polysilicon structure layer and a local oxidation of silicon process is implemented to thermally grow the oxide material using the polysilicon of the structural layer. The second substrate structure may be coupled to the first substrate structure by fusion bonding.

    Abstract translation: MEMS器件包括第一衬底结构和第二衬底结构。 第一衬底结构具有导电微结构和围绕导电微结构的侧面的氧化物材料。 导电微结构的厚度和氧化物材料的厚度大致相等。 第二衬底结构具有MEMS器件的有源区，并且第二衬底结构以与第一衬底结构间隔开的关系耦合以在结构之间产生腔。 MEMS器件的有源区域悬挂在空腔上方，导电微结构位于空腔的下面。 导电微结构由多晶硅结构层形成，并且实施硅工艺的局部氧化以使用结构层的多晶硅热生长氧化物材料。 第二衬底结构可以通过熔融结合耦合到第一衬底结构。

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