公开(公告)号：US07176111B2

公开(公告)日：2007-02-13

申请号：US10263623

申请日：2002-10-03

Applicant: Kris Baert ,  Matty Caymax ,  Cristina Rusu ,  Sherif Sedky ,  Ann Witvrouw

Inventor： Kris Baert ,  Matty Caymax ,  Cristina Rusu ,  Sherif Sedky ,  Ann Witvrouw

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L31/1804 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/017 ,  C23C16/22 ,  G01J5/20 ,  H01L31/09 ,  Y02E10/547 ,  Y02P70/521

Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1−x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Abstract translation: 获得沉积的多晶和低应力SiGe层的方法和装置。 这些层可以用于微机电系统（MEMS）装置或微加工结构中。 分析影响多晶层中的应力的不同参数。 参数包括但不限于：沉积温度; 半导体的浓度（例如，硅和锗在Si 1 x 1-x层中的浓度，x是浓度参数）; 掺杂剂的浓度（例如硼或磷的浓度）; 压力量; 并使用等离子体。 取决于多晶SiGe生长的特定环境，可以使用不同的参数值。

公开(公告)号：US20060166403A1

公开(公告)日：2006-07-27

申请号：US11242960

申请日：2005-10-05

Applicant: Luc Ouellet ,  Robert Antaki

Inventor： Luc Ouellet ,  Robert Antaki

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: B81C1/00246 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0169 ,  B81C2203/0735

Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract translation: 通过在公共衬底上制造包括多个电子部件的电子器件，在公共衬底上制造微电子机械（MEM）器件和电子器件，在电子器件上沉积热稳定的互连层，封装互连 具有保护层的电子器件，在保护层上形成牺牲层，牺牲层中的开孔和保护层，以允许MEM器件与电子器件的连接，通过沉积和图案化制造MEM器件至少一个 非晶硅层，并且去除牺牲层的至少一部分。 以这种方式，MEM装置可以在同一基板上的电子装置之后制造。

公开(公告)号：US20040023429A1

公开(公告)日：2004-02-05

申请号：US10210315

申请日：2002-08-01

Applicant: Motorola Inc.

Inventor： Juergen A. Foerstner ,  Steven M. Smith ,  Raymond Mervin Roop

IPC: H01L021/00

CPC classification number: B81C1/0038 ,  B81B2201/018 ,  B81B2201/0292 ,  B81C1/00246 ,  B81C2201/0164 ,  B81C2203/0735 ,  H01G5/18

Abstract: A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

公开(公告)号：US06522801B1

公开(公告)日：2003-02-18

申请号：US09685883

申请日：2000-10-10

Applicant: Vladimir A. Aksyuk ,  Sungho Jin ,  Jungsang Kim ,  Hareesh Mavoori ,  Flavio Pardo ,  Ainissa Ramirez

Inventor： Vladimir A. Aksyuk ,  Sungho Jin ,  Jungsang Kim ,  Hareesh Mavoori ,  Flavio Pardo ,  Ainissa Ramirez

IPC: G02B642

CPC classification number: G02B26/0841 ,  B81B2201/042 ,  B81B2203/0127 ,  B81C1/00666 ,  B81C2201/0164 ,  G02B6/122 ,  G02B6/266 ,  G02B2006/12104

Abstract: The present invention provides a micro-electro-mechanical system (MEMS) optical device. The micro-electro-mechanical system (MEMS) optical device includes a mirror having a substrate with an implanted light reflective optical layer thereover, and a mounting substrate on which the mirror is movably mounted. The inclusion of the dopant within the light reflective optical layer increases the tensile stress of the device and tends to correct the concave curvature of the mirror structure toward a desirably flat configuration.

Abstract translation: 本发明提供一种微电子机械系统（MEMS）光学装置。 微电子机械系统（MEMS）光学器件包括具有其上具有注入光反射光学层的衬底的反射镜，以及安装衬底，反射镜可移动地安装在该安装衬底上。 掺杂剂在光反射光学层中的包含增加了器件的拉伸应力，并且倾向于将反射镜结构的凹曲线朝向期望的平坦构型进行校正。

公开(公告)号：US20020197762A1

公开(公告)日：2002-12-26

申请号：US10193804

申请日：2002-07-11

Applicant: Microscan systems Incorporated

Inventor： Andrew J. Zosel ,  Joel A. Kubby ,  Jingkuang Chen ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Alex T. Tran

IPC: H01L021/00 ,  H01L021/30 ,  H01L021/46 ,  H01L021/301 ,  H01L021/78

CPC classification number: B81C1/00666 ,  B81B2203/058 ,  B81C2201/014 ,  B81C2201/0164 ,  B81C2201/056 ,  G02B26/0833

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a structure on a single crystal silicon layer separated by an insulator layer from a substrate layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; exposing a selected area of the single crystal silicon layer; and releasing the formed structure.

Abstract translation: 本发明提供一种微机械或微机电结构。 该结构通过包括在衬底层上限定由绝缘体层分离的单晶硅层上的结构的工艺来制造; 沉积和蚀刻单晶硅层上的多晶硅层，其余的聚硅氧烷形成该结构的机械或光学元件; 暴露单晶硅层的选定区域; 并释放形成的结构。

公开(公告)号：US4966663A

公开(公告)日：1990-10-30

申请号：US243816

申请日：1988-09-13

Applicant: Philip E. Mauger

Inventor： Philip E. Mauger

IPC: G01L9/04 ,  C23C14/00 ,  C25F3/12 ,  C30B29/06 ,  C30B31/22 ,  H01L21/265 ,  H01L21/3063 ,  H01L29/84

CPC classification number: B81C1/00666 ,  C23C14/0005 ,  C25F3/12 ,  H01L21/3063 ,  B81B2203/0127 ,  B81C2201/0164 ,  Y10S438/924

Abstract: A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.

Abstract translation: 一种制备具有预定应力特性的硅膜的方法。 掺杂硅衬底以产生如期望的膜厚度那样厚的掺杂层。 通过基于其相对于硅的原子直径选择掺杂剂并控制掺杂剂的总浓度和浓度分布来控制掺杂层内的应力。 然后通过电化学蚀刻掉掺杂层下面的衬底形成膜。

公开(公告)号：US09084067B2

公开(公告)日：2015-07-14

申请号：US13689199

申请日：2012-11-29

Applicant: Yokogawa Electric Corporation

Inventor： Ryuichiro Noda ,  Takashi Yoshida

IPC: H01L41/22 ,  H04R31/00 ,  B81C1/00 ,  H03H3/007

CPC classification number: H04R31/00 ,  B81B2201/0271 ,  B81C1/0015 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/0173 ,  H03H3/0072 ,  Y10T29/49005

Abstract: A method of manufacturing a resonant transducer having a vibration beam includes: (a) providing an SOI substrate including: a first silicon layer; a silicon oxide layer on the first silicon layer; and a second silicon layer on the silicon oxide layer; (b) forming a first gap and second gap through the second silicon layer by etching the second silicon layer using the silicon oxide layer as an etching stop layer; (c) forming an impurity diffusion source layer on the second silicon layer; (d) forming an impurity diffused layer in a surface portion of the second silicon layer; (e) removing the impurity diffusion source layer through etching; and (f) removing at least a portion of the silicon oxide layer through etching such that an air gap is formed between the first silicon layer and a region of the second silicon layer surrounded by the first and second gaps.

Abstract translation: 一种制造具有振动束的谐振换能器的方法包括：（a）提供SOI衬底，包括：第一硅层; 第一硅层上的氧化硅层; 和在氧化硅层上的第二硅层; （b）通过使用氧化硅层作为蚀刻停止层蚀刻第二硅层，形成通过第二硅层的第一间隙和第二间隙; （c）在第二硅层上形成杂质扩散源层; （d）在第二硅层的表面部分形成杂质扩散层; （e）通过蚀刻去除杂质扩散源层; 以及（f）通过蚀刻去除所述氧化硅层的至少一部分，使得在所述第一硅层和由所述第一和第二间隙包围的所述第二硅层的区域之间形成气隙。

公开(公告)号：US20120286903A1

公开(公告)日：2012-11-15

申请号：US13468052

申请日：2012-05-10

Applicant: Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

Inventor： Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

IPC: H01P7/00 ,  G06F17/50

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0177 ,  G06F17/5045 ,  H03H9/02448 ,  H03H9/2447 ,  H03H2009/2442

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract translation: 本发明涉及一种微机械装置，其包括能够偏转或谐振并且包括具有不同材料特性的至少两个区域的半导体元件和功能性耦合到所述半导体元件的驱动或感测装置。 根据本发明，所述区域中的至少一个包括一种或多种n型掺杂剂，并且所述区域的相对体积，掺杂浓度，掺杂剂和/或晶体取向被构造成使得广义刚度的温度敏感度 在区域的至少一个温度下符号相反，半导体元件的整体刚度的总体温度漂移在100℃的温度范围内为50ppm以下。该器件可以是谐振器。 还公开了一种设计该设备的方法。

公开(公告)号：US07371600B2

公开(公告)日：2008-05-13

申请号：US10344006

申请日：2001-06-13

Applicant: Kiyoshi Ishibashi ,  Makio Horikawa ,  Mika Okumura ,  Masaaki Aoto ,  Daisaku Yoshida ,  Hirofumi Takakura

Inventor： Kiyoshi Ishibashi ,  Makio Horikawa ,  Mika Okumura ,  Masaaki Aoto ,  Daisaku Yoshida ,  Hirofumi Takakura

IPC: H01L21/00 ,  H01L29/82

CPC classification number: B81C1/00666 ,  B81B2201/0235 ,  B81C2201/0164 ,  B81C2201/0169 ,  G01P15/125 ,  G01P2015/0814 ,  H01G4/33 ,  H01G5/16

Abstract: A thin-film structural body formed by using a semiconductor processing technique and a manufacturing method thereof, and particularly a thin-film structural body constituting a semiconductor acceleration sensor and a manufacturing method thereof. The thin-film structural body allows the thin-film member to be easily stress-controlled, and easily makes the film-thickness of the thin-film member thicker. The thin-film member forms a mass body and, beams and fixed electrodes of the semiconductor acceleration sensor are constituted by a plurality of doped polysilicon thin-films that are laminated by performing a step of film deposition of polysilicon while, for example, phosphorous is being doped as impurities plural times.

Abstract translation: 通过使用半导体加工技术形成的薄膜结构体及其制造方法，特别是构成半导体加速度传感器的薄膜结构体及其制造方法。 薄膜结构体允许薄膜构件易于受到应力控制，并且容易使薄膜构件的膜厚变厚。 薄膜构件形成质量体，并且半导体加速度传感器的束和固定电极由多个掺杂的多晶硅薄膜构成，所述多个多晶硅薄膜通过执行多晶硅的薄膜沉积步骤而被层压，而例如磷是 作为杂质多次掺杂。

公开(公告)号：US06969425B2

公开(公告)日：2005-11-29

申请号：US10346887

申请日：2003-01-17

Applicant: Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

Inventor： Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/308 ,  H01L29/84 ,  C30B1/10

CPC classification number: B81C1/00365 ,  B81C2201/0164 ,  Y10T428/21 ,  Y10T428/2495

Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.