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    MULTI-CONNECTION VIA
    32.
    发明申请
    MULTI-CONNECTION VIA 审中-公开
    多连接通过

    公开(公告)号：WO0078105A9

    公开(公告)日：2002-06-13

    申请号：PCT/US0015551

    申请日：2000-06-05

    Applicant: TERADYNE INC

    Inventor： KIANI SEPEHR ,  KHUSID MIKHAIL

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/04 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42

    CPC classification number: H05K1/0222 ,  H01R12/523 ,  H05K1/112 ,  H05K1/115 ,  H05K3/043 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09645 ,  H05K2201/1059 ,  H05K2201/10856 ,  H05K2201/10893 ,  H05K2201/10969 ,  H05K2203/0455

    Abstract: An interconnection circuit and related techniques are described. The interconnection circuit (10) includes a plated through hole (26) having a plurality of electrically isolated segments (26a, 26b) with at least one of the plurality of electrically isolated segments (26a) coupled to a signal path (27a, 27b) and at least one of the electrically isolated segments (26b) coupled to the ground (12). With this arrangement, the circuit provides a signal path between a first and a second different layers of a multilayer. By providing one segment (26a) as a signal segment and another segment (26b) as a ground segment the size and shape of the electrically isolated segments (26a, 26b) can be selected to provide the interconnection circuit having a predetermined impedance characteristic. The interconnection circuit can thus be impedance matched to circuit board circuits, devices and transmission lines, such as striplines, microstrips and co-planar waveguides. This results in an interconnection circuit which maintains the integrity of relatively high-frequency signals propagating through the interconnection circuit from the first layer to the second layer. The interconnect circuits can be formed by creating distinct conductor paths (26a, 26b) within the cylindrical plated through-holes (26) using variety of manufacturing techniques including, but not limited to, broaching techniques, electrostatic discharge milling (EDM) techniques and laser etching techniques.

    Abstract translation: 描述了互连电路及相关技术。 互连电路（10）包括具有多个电隔离段（26a，26b）的电镀通孔（26），多个电隔离段（26a）中的至少一个耦合到信号路径（27a，27b） 以及耦合到地（12）的电隔离段（26b）中的至少一个。 利用这种布置，电路提供了多层的第一和第二不同层之间的信号路径。 通过提供作为信号段的一个段（26a）和作为接地段的另一段（26b），可以选择电隔离段（26a，26b）的大小和形状，以提供具有预定阻抗特性的互连电路。 因此，互连电路可以与电路板电路，器件和传输线（例如带状线，微带和共面波导）阻抗匹配。 这导致互连电路，其维持通过互连电路从第一层传播到第二层的相对高频信号的完整性。 互连电路可以通过使用各种制造技术在圆柱形电镀通孔（26）内形成不同的导体路径（26a，26b）来形成，包括但不限于拉削技术，静电放电铣削（EDM）技术和激光 蚀刻技术。

    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS
    33.
    发明申请
    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS 审中-公开
    装有内层的装置支持表面装配组件

    公开(公告)号：WO9524730A3

    公开(公告)日：1996-02-15

    申请号：PCT/US9502678

    申请日：1995-03-09

    Applicant: PANDA PROJECT

    Inventor： CRANE STANFORD W JR ,  PORTUONDO MARIA M

    IPC: H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/46 ,  H01L

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: An apparatus comprising a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire (11) extending into the well (15) and being in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire (11) from a device into the well (15) such that the lead or wire is in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate.

    Abstract translation: 半导体管芯封装（30）包括多个导电引线（11）和用于承载电信号的多层结构（10），所述多层结构（10）包括多层绝缘材料（12a-12d ），每个层包括在该层的相对侧上的第一表面和第二表面。 每个引线（11）延伸到完全延伸通过至少一个层的相应的阱（15），并且在一个层的一个表面上底部，阱（15）不通过该表面延伸并电耦合 涉及形成在其对应的井（15）内的导电接合结构（13）。

    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS
    34.
    发明申请
    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS 审中-公开
    装有内层的装置支持表面装配组件

    公开(公告)号：WO1995024730A2

    公开(公告)日：1995-09-14

    申请号：PCT/US1995002678

    申请日：1995-03-09

    Applicant: THE PANDA PROJECT

    Inventor： THE PANDA PROJECT ,  CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M.

    IPC: H01L00/00

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: An apparatus comprising a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire extending into the well and being in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire from a device into the well such that the lead or wire is in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate.

    Abstract translation: 一种包括多层衬底的装置，所述多层衬底包括多层绝缘材料，至少一个阱形成在至少一层中，所述阱从所述多层衬底的外表面延伸到所述多层衬底的内表面 以及在所述多层基板的内表面上的所述阱内形成的导电部件; 以及具有延伸到阱中的至少一个导电引线或导线并与形成在多层基板的内表面上的导电部件直接物理接触的器件。 另外，制造装置的方法包括以下步骤：形成包括多层绝缘材料的多层基板，至少一层形成在至少一层中的阱，所述阱从多层的外表面延伸 在多层基板的内表面上形成有在多层基板的内表面上的导电部件， 并且将至少一个导电引线或线从器件延伸到阱中，使得引线或引线与形成在多层衬底的内表面上的导电部件直接物理接触。

    표면-장착구성요소를지지하는내부층을가지는기구
    37.
    发明授权
    표면-장착구성요소를지지하는내부층을가지는기구 失效
    표면 - 장착구성요소를지지하는내부층을가지는기구

    公开(公告)号：KR100367045B1

    公开(公告)日：2003-04-10

    申请号：KR1019960705039

    申请日：1995-03-09

    Applicant: 더 판다 프로젝트

    Inventor： 크레인,스탠포드,더블유.,제이알. ,  포르투온도,마리아,엠.

    IPC: H05K3/34 ,  H05K3/40

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: 복수 개의 절연 물질층과, 상기 층 중의 최소한 한 층에 형성되고 다층 기판의 외부 표면에서 부터 다층 기판의 내부 면까지 뻗는 최소한 하나의 웰과, 다층 기판 내부 면의 웰내에 형성된 전기적으로 도전성이 있는 구성 요소를 포함하는 다층 기판, 및 상기 웰내로 뻗은 최소한 하나의 전기적으로 도전성이 있는 리이드 또는 와이어를 가지며 다층 기판 내부 면에 형성된 전기적으로 도전성이 있는 구성 요소와 직접 물리적 접촉을 하는 소자를 구비하는 것을 특징으로 하는 기구.
    또한, 복수 개의 절연 물질층과 상기 층 중의 최소한 한 층에 형성된 다층 기판의 외부 표면에서 부터 다층 기판의 내부 면까지 뻗는 최소한 하나의 웰과 다층 기판 내부 면의 웰내에 형성된 전기적으로 도전성이 있는 구성 요소를 포함하는 다층 기판을 형성하는 단계; 및 소자에서 나온 최소한 하나의 전기적으로 도전성이 있는 리이드 또는 와이어를 상기 웰내로 뻗게 하여, 상기 리이드 또는 와이어가 다층 기판의 내부 면 위에 형성된 전기적으로 도전성이 있는 구성 요소와 직접 물리적 접촉을 하도록 하는 단계를 구비하는 것을 특징으로 하는 기구 제조 방법.

    Abstract translation: 半导体管芯封装（30）包括多个导电引线（11）和用于承载电信号的多层结构（10），所述多层结构（10）包括多个绝缘材料层（12a-12d） ），所述层中的每一个包括在所述层的相对侧上的第一表面和第二表面。 每个引线（11）延伸到相应的阱（15）中，该阱完全延伸穿过至少一个层并且在阱（15）未延伸穿过的层中的一个的表面之一的底部处达到底部并且电耦合 连接到形成在其相应的井（15）内的导电接合结构（13）。 ＆lt;图像＆GT;

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