公开(公告)号：US20230017764A1

公开(公告)日：2023-01-19

申请号：US17947682

申请日：2022-09-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jie LUO ,  Deyuan XIAO

IPC: H01L27/108

Abstract: A semiconductor structure and a method for preparing a semiconductor structure are provided. The semiconductor structure includes a substrate. A first active area, a second active area and an isolation structure are arranged on the substrate. The first active area and the second active area are isolated from one another by the isolation structure. The first active area includes a first doped region and a second doped region. The second active area includes a third doped region and a fourth doped region. The semiconductor structure further includes a gate structure. The gate structure is arranged above the second doped region and the third doped region, and the gate structure is connected to the second doped region and the third doped region.

公开(公告)号：US20220416049A1

公开(公告)日：2022-12-29

申请号：US17897242

申请日：2022-08-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Guangsu SHAO ,  Deyuan XIAO ,  Weiping BAI ,  Yunsong QIU

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Embodiments disclose a semiconductor structure and a fabrication method thereof. The method includes: providing a substrate; forming a stack structure on a surface of the substrate, where the stack structure includes a first semiconductor material layer and a first sacrificial layer alternately stacked from bottom to top; patterning and etching the stack structure and removing part of the first sacrificial layer to form a horizontal strip-shaped structure; forming a gate-all-around structure, where the gate-all-around structure covers part of a surface of the horizontal strip-shaped structure; and forming a bit line, where the bit line is formed in a same horizontal plane as the horizontal strip-shaped structure and the horizontal strip-shaped structure is segmented by the bit line, and the bit line is connected to a segmentation of the horizontal strip-shaped structure.

公开(公告)号：US20250149339A1

公开(公告)日：2025-05-08

申请号：US18398558

申请日：2023-12-28

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng Gao ,  Shuai Yang ,  Jinbiao Liu ,  Weibing Liu ,  Junfeng Li ,  Jun Luo ,  Jinjuan Xiang

IPC: H01L21/225 ,  H01L21/02

Abstract: A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

公开(公告)号：US12238918B1

公开(公告)日：2025-02-25

申请号：US18754418

申请日：2024-06-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Wenhua Gui ,  Xuezheng Ai ,  Guilei Wang ,  Jin Dai ,  Xiangsheng Wang

IPC: H10B12/00

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

公开(公告)号：US12235766B2

公开(公告)日：2025-02-25

申请号：US18609230

申请日：2024-03-19

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jin Dai

IPC: G06F12/0817 ,  G06F3/06

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

公开(公告)号：US20240130106A1

公开(公告)日：2024-04-18

申请号：US18304219

申请日：2023-04-20

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jin DAI ,  Yong YU ,  Jing LIANG

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

公开(公告)号：US11928345B1

公开(公告)日：2024-03-12

申请号：US18312968

申请日：2023-05-05

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jin Dai ,  Yunsen Zhang

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0679

Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.

公开(公告)号：US20230343851A1

公开(公告)日：2023-10-26

申请号：US17783624

申请日：2021-12-23

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Weixing HUANG ,  Huilong ZHU

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/1033 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are sequentially formed on a substrate. Then, a part of the semiconductor layer is removed through etching a sidewall of the semiconductor layer to form a cavity. Afterwards, a channel layer is formed at the cavity, a sidewall of the first electrode layer, and a sidewall of the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. Then, a part of the dummy gate layer is removed through etching a sidewall of the dummy gate layer with the second channel part serving as a shield. Afterwards, the second channel part and the first channel part, which is in contact with an upper surface and a lower surface of the dummy gate layer, are removed to form a recess. The recess is formed by either the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer. The recess is filled with a dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce parasitic capacitance of the semiconductor device and improve a performance of the semiconductor device.

公开(公告)号：US20230320071A1

公开(公告)日：2023-10-05

申请号：US18141107

申请日：2023-04-28

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： Zhengyong Zhu ,  Bokmoon Kang ,  Guilei Wang ,  Chao Zhao

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing “1” and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting the size of the output current of the field effect transistor.

公开(公告)号：US20230320070A1

公开(公告)日：2023-10-05

申请号：US18139766

申请日：2023-04-26

Applicant: Beijing Superstring Academy of Memory Technology

Inventor： Zhengyong Zhu ,  Bokmoon Kang ,  Guilei Wang ,  Chao Zhao

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.