41.
    发明专利
    未知

    公开(公告)号:AT362262T

    公开(公告)日:2007-06-15

    申请号:AT03713861

    申请日:2003-03-04

    Abstract: A resonant power converter (220) for ultra-efficient radio frequency transmission and associated methods is disclosed. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder (222), a charging switch (224), and a high-Q resonator (204) coupled to an output load (206), typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load (206) with very little wasted energy in the process. No active power amplifier is required. The apparatus (220) can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

    43.
    发明专利
    未知

    公开(公告)号:DE60119889T2

    公开(公告)日:2007-04-26

    申请号:DE60119889

    申请日:2001-04-02

    Abstract: The analogue signal analogue to digital conversion method has a mobile telephone reception stage with a delta sigma parameterable converter (CAN). During transmission converter parameters are adjusted as a function of the transmission index of digital conditions and real reception conditions.

    46.
    发明专利
    未知

    公开(公告)号:DE60308133D1

    公开(公告)日:2006-10-19

    申请号:DE60308133

    申请日:2003-01-10

    Abstract: The device has an input terminal (BE) to receive a signal. Delta-sigma power amplification unit (MAP) comprises signal amplifiers respectively connected between the terminal and an adder (ADD). The adder is disposed between a frequency selector (INT1, INT2) and quantification unit. Values of the signal gain are adjusted in order to place zeros in a signal transfer function. An Independent claim is also included for a communication system.

    47.
    发明专利
    未知

    公开(公告)号:DE50108998D1

    公开(公告)日:2006-04-27

    申请号:DE50108998

    申请日:2001-12-18

    Inventor: BENTHIEN STEPHAN

    Abstract: The invention relates to an image sensor device comprising a substrate, formed in CMOS technology, in particular, with an integrated semiconductor structure (ASIC) and, arranged above that, an optically active thin-film structure comprising in each case at least one layer made of doped and undoped amorphous silicon, spatially adjacent pixels in each case being formed in the horizontal plane, which pixels each have an optoelectronic transducer for converting incident light into an electric current proportional to the incident quantity of light, and also a charge store assigned to the optoelectronic transducer, the charge state of which charge store can be varied in a manner dependent on the light incident on the assigned optoelectronic transducer. Taking this as a departure point, the invention is based on the object of further developing an image sensor device of the stated type to the effect of avoiding image distortions in the case of moving objects, which is achieved according to the invention by virtue of the fact that the charge store is a capacitor (C int ), in which the photocurrent output by the optoelectronic transducer can be integrated during a predetermined measurement duration, and that a switching means (T stop ) that can be driven by a common control device is provided in each pixel, which switching means can be driven jointly for all the pixels of the image sensor device.

    48.
    发明专利
    未知

    公开(公告)号:DE69922176T2

    公开(公告)日:2005-11-10

    申请号:DE69922176

    申请日:1999-02-17

    Abstract: Zipper is the time-synchronized frequency-division duplex implementation of discrete multi-tome (DMT) modulation. Two communicating Zipper modems transmit DMT symbols simultaneously with a common clock. When all transmitters are time synchronized, the near end cross-talk (NEXT) and near end echoes injected into the received signal are orthogonal to the desired signal. The present invention provides a telecommunications transmission system using zipper and having at least two VDSL systems. Each VDSL system comprises a pair of zipper modems communicating over a cable transmission path. The telecommunications transmission system handles zipper transmission transmitted over the common cable; at least partly mitigates NEXT; and permits transmissions in a first VDSL system which are asynchronous with transmissions in a second VDSL system.

    49.
    发明专利
    未知

    公开(公告)号:DE69915082D1

    公开(公告)日:2004-04-01

    申请号:DE69915082

    申请日:1999-12-14

    Abstract: The invention relates to a far-end crosstalk (FEXT) canceling circuit for a digital subscriber line transmission system, said transmission system comprising a plurality n of line termination (LT) modems (Mi) transmitting discrete multitone (DMT) symbols Si to corresponding network (NT) termination modems (Mc(i)) over n transmission channels. The invention proposes to multiply the vector S = (Si) i = 1 to n, before transmission, by a precompensation matrix M such that the matrix product H*M is diagonal, H being the transfer matrix of the n downstream transmission channels defined by R = H*S where R = (Ri), i = 1 to n, is the vector of the DMT symbols Ri respectively received by the modems Mc(i).

    50.
    发明专利
    未知

    公开(公告)号:DE69905040T2

    公开(公告)日:2004-01-22

    申请号:DE69905040

    申请日:1999-05-11

    Abstract: In a multi-carrier system employing OFDM, for example DMT, an adaptive channel equalizer is normally used, operating in the frequency domain. The sampling clock is controlled so that the time delay between the transmitter and the receiver is effectively eliminated. If the information used to control the sampling clock is received from the equalized data stream, it will introduce an ambiguity between the operation of the channel equalizer and the mechanism used to control the sampling clock. Operation of the equalizer can mask an increasing time difference, between transmitter and receiver, which the sample clock controller should be tracking. The present invention eliminates the ambiguities in the operation of the equalizer and sample clock controller by preventing the equalizer accepting time differences which should be corrected by operation of the sample clock controller.

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