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公开(公告)号：KR1020100061290A
公开(公告)日：2010-06-07
申请号：KR1020090038461
申请日：2009-04-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1225 , H01L27/092 , H01L27/1251
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a performance characteristic of the device by reducing a resistance with forming a p+ domain on the central part of a first oxide channel layer. CONSTITUTION: A first oxide channel layer(C10) is formed into a first conductive type oxide on a lower part layer. A first electrode layer covering the first channel layer is formed on the lower part layer. The first electrode layer and a second electrode layer separated are formed. A second oxide channel layer(C20) is formed into a second conductive type oxide on the lower part later. The first electrode layer is patterned. A first source, a first drain and the second drain are formed by the patterning of the first electrode layer.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过在第一氧化物沟道层的中心部分形成p +畴来降低电阻来提高器件的性能特性。 构成：第一氧化物沟道层（C10）在下部层上形成为第一导电型氧化物。 覆盖第一沟道层的第一电极层形成在下部层上。 形成分离的第一电极层和第二电极层。 第二氧化物沟道层（C20）稍后在下部形成第二导电型氧化物。 图案化第一电极层。 通过图案化第一电极层形成第一源极，第一漏极和第二漏极。
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公开(公告)号：KR1020100040580A
公开(公告)日：2010-04-20
申请号：KR1020080099778
申请日：2008-10-10
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L21/8239
CPC classification number: G11C5/02 , G11C5/143 , G11C7/18 , G11C8/12 , G11C13/0023 , G11C2213/71
Abstract: PURPOSE: A stacked memory device is provided to reduce the area in which the stacked memory device is occupied by stacking active circuit parts between memory layers. CONSTITUTION: Stacked memory layers(110) include memory cell array. A first active circuit part(140) processes the address information of the memory cell array which is divided into vertical address information and horizontal address information. A second active circuit part(160) is arranged on the first active circuit part. The second active circuit part generates memory selection signal to each memory cell based on the processed signal of the first active circuit parts. The first active circuit part includes a level decoder(120) and a pre decoder(130). The level decoder decodes the vertical address information. The pre decoder decodes the horizontal address information.
Abstract translation: 目的：提供堆叠的存储器件，以通过在存储器层之间堆叠有源电路部分来减少堆叠的存储器件被占用的区域。 构成：堆叠的存储器层（110）包括存储单元阵列。 第一有源电路部分（140）处理被划分为垂直地址信息和水平地址信息的存储单元阵列的地址信息。 第二有源电路部分（160）布置在第一有源电路部分上。 第二有源电路部分基于第一有源电路部分的处理信号，向每个存储器单元产生存储器选择信号。 第一有源电路部分包括电平解码器（120）和预解码器（130）。 电平解码器解码垂直地址信息。 预解码器解码水平地址信息。
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公开(公告)号：KR1020100038714A
公开(公告)日：2010-04-15
申请号：KR1020080097786
申请日：2008-10-06
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
CPC classification number: G11C8/06 , G06F12/0238 , G06F2212/7201 , G11C13/0069
Abstract: PURPOSE: An operation method of a nonvolatile memory is provided to improve the reliability of a nonvolatile memory status by transiting the state of a nonvolatile memory to only one side direction. CONSTITUTION: The first logical address and the first physical address are written in the specific row of a look-up table(LUT). First data is programmed in data storage area which the first physical address points the first logical address(LA) is mapped. A first logical address and a second physical address(PA) are written in the other row of the look-up table. Second data is programmed in data storage area which the second physical address points.
Abstract translation: 目的：提供一种非易失性存储器的操作方法，以通过将非易失性存储器的状态转换为仅一个侧面方向来提高非易失性存储器状态的可靠性。 构成：第一个逻辑地址和第一个物理地址被写入查找表（LUT）的特定行。 第一数据被编程在数据存储区域中，第一物理地址指向第一逻辑地址（LA）被映射。 第一逻辑地址和第二物理地址（PA）被写入查找表的另一行。 第二数据被编程在第二物理地址指向的数据存储区中。
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公开(公告)号：KR1020100007703A
公开(公告)日：2010-01-22
申请号：KR1020090033846
申请日：2009-04-17
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/78696 , H01L29/41725 , H01L29/42312 , H01L29/7869
Abstract: PURPOSE: A channel layer and a transistor including the same are provided to control a threshold voltage and the mobility of a transistor by comprising the channel layer with a first layer and a second layer with different carrier density and/or mobility. CONSTITUTION: A transistor includes a channel layer(C1), a source(S1), a drain(D1), and a gate(G1). The channel layer has different mobility and includes a lower layer(10) and an upper layer(20). The lower layer and the upper layer are made of the different oxide. The source and the drain are contacted with both sides of the channel layer. The gate applies the electric field to the channel layer. The closest layer to the gate among the lower layer and the upper layer determines the mobility of the transistor.
Abstract translation: 目的：提供沟道层和包括该沟道层的晶体管，以通过包括具有不同载流子密度和/或迁移率的第一层和第二层的沟道层来控制晶体管的阈值电压和迁移率。 构成：晶体管包括沟道层（C1），源极（S1），漏极（D1）和栅极（G1）。 沟道层具有不同的迁移率，并且包括下层（10）和上层（20）。 下层和上层由不同的氧化物制成。 源极和漏极与沟道层的两侧接触。 栅极将电场施加到沟道层。 下层和上层之间最靠近栅极的层决定了晶体管的迁移率。
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公开(公告)号：KR1020100000650A
公开(公告)日：2010-01-06
申请号：KR1020080060228
申请日：2008-06-25
Applicant: 삼성전자주식회사
CPC classification number: H01L29/0665 , B82Y10/00 , H01L27/1214 , H01L29/0673 , H01L29/0676 , H01L29/7869 , H01L33/18 , H01L33/28
Abstract: PURPOSE: A display device using an oxide diode is provide to improve a life and light emitting efficiency by forming a plurality of nano rod diodes on a plug metal layer. CONSTITUTION: A display device includes a substrate, a thin film transistor layer(20), and a light emitting layer(30). The thin film transistor layer is formed on the substrate. The light emitting layer includes a plug metal layer(31), a plurality of nano rod diodes(34), and a transparent electrode(35). The plug metal layer is formed on the thin film transistor layer. The plurality of nano rod diodes are vertically formed on the plug metal layer. The transparent electrode is formed on the plurality of nano rod diodes. Each nano rod diode includes a lower layer part, an upper layer part, and a non-doped region.
Abstract translation: 目的：使用氧化二极管的显示装置用于通过在插塞金属层上形成多个纳米棒状二极管来提高寿命和发光效率。 构成：显示装置包括基板，薄膜晶体管层（20）和发光层（30）。 薄膜晶体管层形成在基板上。 发光层包括插塞金属层（31），多个纳米棒状二极管（34）和透明电极（35）。 插塞金属层形成在薄膜晶体管层上。 多个纳米棒状二极管垂直地形成在插塞金属层上。 透明电极形成在多个纳米棒状二极管上。 每个纳米棒二极管包括下层部分，上层部分和非掺杂区域。
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Patent Agency Ranking
公开(公告)号：KR1020090131555A
公开(公告)日：2009-12-29
申请号：KR1020080057488
申请日：2008-06-18
Applicant: 삼성전자주식회사
CPC classification number: H03K19/01714
Abstract: PURPOSE: An inverter device and an operating method thereof are provided to perform a high operation speed by enhancing an output voltage through a first parasitic capacitance of a load transistor. CONSTITUTION: A first transistor(T10) applies a power voltage to a first drain(D1), and outputs an output voltage from a first source(S1). A second transistor(T20) applies an input voltage to a second gate(G2), and connects a second drain(D2) to the first source in order to output the output voltage. A third transistor(T30) applies a power voltage to a third gate and a third drain(D3), and connects a third source(S3) to the first gate. The first gate and the first source capacitively couple the first transistor.
Abstract translation: 目的：通过增加负载晶体管的第一寄生电容的输出电压，提供逆变器装置及其操作方法来执行高操作速度。 构成：第一晶体管（T10）将电源电压施加到第一漏极（D1），并输出来自第一源极（S1）的输出电压。 第二晶体管（T20）将输入电压施加到第二栅极（G2），并且将第二漏极（D2）连接到第一源极以输出输出电压。 第三晶体管（T30）将电源电压施加到第三栅极和第三漏极（D3），并将第三源极（S3）连接到第一栅极。 第一个栅极和第一个源极电容耦合第一个晶体管。
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公开(公告)号：KR1020090119666A
公开(公告)日：2009-11-19
申请号：KR1020080096027
申请日：2008-09-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L27/1225 , H01L27/1251 , H01L29/66969 , H01L29/78621 , H01L29/78648 , H01L29/78696
Abstract: PURPOSE: A semiconductor device and a method of manufacturing the same are provided to make manufacturing costs simple and reduce manufacturing costs by forming a source area and a drain area in plasma process. CONSTITUTION: In a semiconductor device and a method of manufacturing the same, a semiconductor device including a thin film transistor is composed of a first oxide semiconductor layer and a first lamination structure. The first oxide semiconductor layer is formed on the substrate(SUB1). The first oxide semiconductor layer has the first source areas between the first channel area and the first drain area. The first lamination structures include a first channel region where a first gate isolation layers and a first gate electrode which are sequentially laminated.
Abstract translation: 目的：提供半导体器件及其制造方法，通过在等离子体工艺中形成源极区域和漏极区域，使制造成本简单并降低制造成本。 构成：在半导体器件及其制造方法中，包括薄膜晶体管的半导体器件由第一氧化物半导体层和第一层叠结构构成。 第一氧化物半导体层形成在基板（SUB1）上。 第一氧化物半导体层具有在第一沟道区和第一漏区之间的第一源区。 第一层叠结构包括第一沟道区，其中第一栅极隔离层和第一栅极电极依次层叠。
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公开(公告)号：KR1020090001368A
公开(公告)日：2009-01-08
申请号：KR1020070065684
申请日：2007-06-29
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/2436 , H01L27/2463
Abstract: The non-volatile semiconductor device is provided to reduce the size of the selecting transistor by forming the selecting transistor in the memory cells and the other layer and then the contact in the selecting transistor. The non-volatile semiconductor device comprises the semiconductor substrate(230), and a plurality of memory cells(WP1-WPn) formed on the semiconductor substrate. One or more selecting transistor(GSLP,SSLP) is formed on the semiconductor substrate. The selecting transistor is formed in the memory cells and the other layer. One or more selecting transistor comprises the first contact which connects the dataline or the power line to the selecting transistor and the second contact which connects the selecting transistor and memory cells. The first contact connects the dataline or the power line to the selecting transistor through the first doped region of the semiconductor substrate. One or more selecting transistor comprises the first selecting transistor and the second selection transistor.
Abstract translation: 提供非易失性半导体器件以通过在存储单元中形成选择晶体管，而在另一层中形成选择晶体管，然后在选择晶体管中形成接触来减小选择晶体管的尺寸。 非易失性半导体器件包括半导体衬底（230）和形成在半导体衬底上的多个存储单元（WP1-WPn）。 在半导体衬底上形成一个或多个选择晶体管（GSLP，SSLP）。 选择晶体管形成在存储单元和另一层中。 一个或多个选择晶体管包括将数据线或电源线连接到选择晶体管的第一触点和连接选择晶体管和存储单元的第二触点。 第一个触点通过半导体衬底的第一掺杂区将数据线或电源线连接到选择晶体管。 一个或多个选择晶体管包括第一选择晶体管和第二选择晶体管。
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公开(公告)号：KR1020080076608A
公开(公告)日：2008-08-20
申请号：KR1020070016778
申请日：2007-02-16
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L29/78609
Abstract: A thin film transistor and a fabricating method thereof are provided to prevent a channel layer made of oxide semiconductor material from damaging and suppress a deterioration of property by covering a part of the channel layer with a protection layer. A thin film transistor comprises a channel layer(110), source and drain electrodes(130a,130b), a protection layer(120), a gate electrode(150), and a gate insulation layer(140). The channel is formed of an oxide semiconductor material. The source and drain electrode face each other on the channel layer. The protection layer covers the channel under the source and drain electrodes. The gate electrode applies an electric field to the channel layer. The gate insulation layer is disposed between the gate electrode and the channel layer. The channel layer is a ZnO based material layer. The channel layer a(In2O3), b(Ga2O3), and c(ZnO), wherein a, b, and c meets the terms of a>=0, b>=0, and c>0.
Abstract translation: 提供薄膜晶体管及其制造方法，以防止由氧化物半导体材料制成的沟道层损坏并通过用保护层覆盖沟道层的一部分来抑制性能的劣化。 薄膜晶体管包括沟道层（110），源极和漏极（130a，130b），保护层（120），栅极电极（150）和栅极绝缘层（140）。 通道由氧化物半导体材料形成。 源极和漏极在沟道层上彼此面对。 保护层覆盖源极和漏极下的沟道。 栅电极向沟道层施加电场。 栅极绝缘层设置在栅电极和沟道层之间。 沟道层是ZnO基材料层。 通道层a（In2O3），b（Ga2O3）和c（ZnO），其中a，b和c满足a> = 0，b> = 0和c> 0的项。
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公开(公告)号：KR100207618B1
公开(公告)日：1999-07-15
申请号：KR1019930018356
申请日：1993-09-13
Applicant: 삼성전자주식회사
IPC: H01M10/00
Abstract: 2차전지의 음극 제조방법 및 이를 갖는 2차전지가 개시된다. Ti+Ni을 적어도 40 원자% 이상 함유한 수소저장합금을 분쇄하고 기판상에 충전하는 단계를 포함하는 2차전지의 음극 제조방법에 있어서, 상기 수소저장합금을 700 내지 1350℃ 온도 범위에서 1 내지 80시간 동안 열처리하는 단계, 및 상기 열처리한 수소저장합금을 분쇄한 다음에 슬러리로 제조하여 기판상에 충전하고 압착하는 단계를 포함하는 2차전지의 음극 제조방법에 따라 제조된 음극을 갖는 2차전지의 내압 특성 및 내구성이 향상되고 급속충방전이 가능하게 된 우수한 것이다.
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