公开(公告)号：KR100734304B1

公开(公告)日：2007-07-02

申请号：KR1020060004439

申请日：2006-01-16

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  김창현

IPC: H01L21/8242

Abstract: A method for manufacturing a transistor is provided to manufacture the transistor having improved charge storing ability by minimizing contact area between a channel body and a source region/drain region, maximizing dimension of the channel body, and forming a back gate electrode. First conductive-type impurity ion is implanted into a first surface of a first semiconductor substrate to form a first impurity region(110) under the first surface of the semiconductor substrate. A mask pattern(125) having a predetermined width is formed on the first impurity region. A part of the first impurity region is etched by using the mask pattern as an etching mask to form a protrusion of a first impurity region on a lower portion of the mask pattern. A planarized insulating material layer(152) is formed on the first impurity region including the protrusion. A second semiconductor substrate(162) is bonded on the planarized insulating material layer. A part of the first semiconductor substrate is removed from a second surface of the first semiconductor substrate so that the first impurity region in the first semiconductor substrate is exposed. A gate electric pattern is formed on the exposed first impurity region so that the protrusion of the first impurity region is located on a lower portion thereof. Second conductive type impurity ion is implanted into the first impurity region by using the gate electric pattern as an ion implantation mask to form source region/drain regions(143,144).

Abstract translation: 提供一种用于制造晶体管的方法，通过最小化沟道体与源极区/漏极区之间的接触面积，使沟道体的尺寸最大化并形成背栅电极，来制造具有改善的电荷存储能力的晶体管。 将第一导电型杂质离子注入到第一半导体衬底的第一表面中，以在半导体衬底的第一表面下方形成第一杂质区域（110）。 具有预定宽度的掩模图案（125）形成在第一杂质区域上。 通过使用掩模图案作为蚀刻掩模来蚀刻第一杂质区域的一部分，以在掩模图案的下部形成第一杂质区域的突起。 平坦化绝缘材料层（152）形成在包括突起的第一杂质区域上。 第二半导体衬底（162）结合在平坦化的绝缘材料层上。 第一半导体衬底的一部分从第一半导体衬底的第二表面去除，使得第一半导体衬底中的第一杂质区域暴露。 栅电图案形成在暴露的第一杂质区上，使得第一杂质区的突起位于其下部。 通过使用栅极电图形作为离子注入掩模将第二导电类型杂质离子注入到第一杂质区中以形成源极区/漏极区（143,144）。

公开(公告)号：KR100697291B1

公开(公告)日：2007-03-20

申请号：KR1020050086443

申请日：2005-09-15

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  박병국

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926 ,  H01L21/28273 ,  H01L21/28282

Abstract: A non-volatile semiconductor memory device and a method for fabricating the same are provided to enhance a degree of integration by doubling data storage capacity within the same size. A plurality of pillars(20) are projected from a surface of a semiconductor substrate. A plurality of bit lines(BL) are formed on an upper surface of the pillars to connect pillars in one direction. A plurality of word lines(WL) are formed vertically to the bit lines on both sides of the pillars. A plurality of memory layers(30) are formed between the pillars and the word lines. A plurality of drain regions are formed on upper ends of the pillars. A plurality of source regions are formed on lower ends of the pillars. The source regions are entirely connected with each other.

Abstract translation: 提供了一种非易失性半导体存储器件及其制造方法，以通过将相同尺寸的数据存储容量加倍来增强集成度。 多个柱（20）从半导体衬底的表面突出。 在柱的上表面上形成多个位线（BL），以在一个方向上连接支柱。 多个字线（WL）垂直于立柱两侧的位线形成。 在柱和字线之间形成多个存储层（30）。 在柱的上端形成有多个漏区。 多个源区形成在支柱的下端。 源区域彼此完全连接。

公开(公告)号：KR100678643B1

公开(公告)日：2007-02-05

申请号：KR1020050124005

申请日：2005-12-15

Applicant: 삼성전자주식회사

Inventor： 송기환

IPC: G11C11/403

Abstract: A multi-level dynamic memory device is provided to maintain constant amount of charges between a main bit line pair and a sub bit line pair through first and second compensation capacitors, and to reduce restore errors by using a dummy memory cell. A bit line pair is divided into a main bit line pair(BLM,BLBM) and a sub bit line pair(BLs,BLBs). A first sense amplifier(SAM) is connected between the main bit line pair, and a second sense amplifier(SAS) is connected between the sub bit line pair. First and second coupling capacitors(Cc1,Cc2) are cross-coupled between the main bit line pair and the sub bit line pair. First and second compensation capacitors(Ccal1,Ccal2) are connected to the first and second coupling capacitors in parallel, respectively, and have capacitance controlled by a control voltage signal.

Abstract translation: 提供多级动态存储器件以通过第一和第二补偿电容器在主位线对和子位线对之间保持恒定的电荷量，并且通过使用伪存储器单元来减少恢复错误。 位线对被分成主位线对（BLM，BLBM）和子位线对（BLs，BLB）。 第一读出放大器（SAM）连接在主位线对之间，并且第二读出放大器（SAS）连接在子位线对之间。 第一和第二耦合电容器（Cc1，Cc2）交叉耦合在主位线对和子位线对之间。 第一和第二补偿电容器（Ccal1，Ccal2）分别并联连接到第一和第二耦合电容器，并且具有由控制电压信号控制的电容。

公开(公告)号：KR100660910B1

公开(公告)日：2006-12-26

申请号：KR1020060002378

申请日：2006-01-09

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  정훈

IPC: H01L27/108

Abstract: A capacitor-less DRAM and its manufacturing method are provided to increase a charge storing capacity of a channel body and to reduce the leak of charges through a junction region between the channel body and source/drain using a pair of cylinder type auxiliary gates. An isolation layer is formed on a semiconductor substrate(100). A pair of plug nodes(120) are spaced apart from each other in the substrate. An upper surface of each plug node is exposed to the outside. A pair of cylinder type auxiliary gates(122) are connected to a lower portion of each plug node in the substrate. The cylinder type auxiliary gates are connected with each other. A source and a drain(103) are spaced apart from each other in the substrate. A channel body(104) is formed between the source and the drain. A main gate(130) is arranged on the channel body and insulated from the substrate.

Abstract translation: 提供一种无电容DRAM及其制造方法，以增加沟道体的电荷存储容量，并且减少通过沟道体与源极/漏极之间的结区域的电荷泄漏，其使用一对圆柱型辅助栅极。 隔离层形成在半导体衬底（100）上。 一对插头节点（120）在衬底中彼此间隔开。 每个插头节点的上表面暴露于外部。 一对圆柱型辅助闸门（122）连接到基板中每个插头节点的下部。 缸式辅助门相互连接。 源极和漏极（103）在衬底中彼此间隔开。 通道主体（104）形成在源极和漏极之间。 主通道（130）布置在通道主体上并与基底绝缘。

公开(公告)号：KR100493020B1

公开(公告)日：2005-06-07

申请号：KR1020020038890

申请日：2002-07-05

Applicant: 삼성전자주식회사

Inventor： 송호성 ,  송기환 ,  이동수

IPC: G11C11/40

CPC classification number: G11C7/1057 ,  G11C7/1051

Abstract: 고 주파수 동작을 위한 출력 드라이버를 구비하는 반도체 메모리 장치가 개시된다. 본 발명에 따른 반도체 메모리 장치는, 제 1 및 제 2 엔모스 트랜지스터가 직렬로 연결되며, 상기 제 1 엔모스 트랜지스터의 드레인이 출력 패드에 연결되고, 상기 제 2 엔모스 트랜지스터의 소스가 접지 전압에 연결되는 출력 드라이버를 구비하는 반도체 메모리 장치에 있어서, 상기 제 1 엔모스 트랜지스터의 게이트로 제 1 내부 전압이 인가되고 상기 제 2 엔모스 트랜지스터의 게이트로 제 2 내부 전압이 인가되며, 상기 제 2 내부 전압은 외부 전원 전압보다 낮은 전압 레벨을 가지는 것을 특징으로 한다. 상기 제 2 내부 전압은 상기 메모리 장치의 내부의 내부 전압 발생 회로로부터 발생되거나 또는 상기 메모리 장치의 외부에서 직접 인가되는 것을 특징으로 한다. 상기 제 2 내부 전압의 전압 레벨은 상기 반도체 메모리 장치의 동작 전압 레벨과 다를 수 있다.
상술한 바와 같이 본 발명에 따른 반도체 메모리 장치는 높은 주파수를 가지는 데이터를 파형의 왜곡 없이 출력할 수 있으므로 좋은 출력 특성과 큰 타이밍 마진을 확보할 수 있는 장점이 있다.

公开(公告)号：KR100413761B1

公开(公告)日：2003-12-31

申请号：KR1020010030522

申请日：2001-05-31

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  송호성

IPC: G11C11/401

CPC classification number: G11C7/04 ,  G11C7/22 ,  G11C7/222

Abstract: Clock generation circuits for an integrated circuit device are provided including a temperature sensor circuit, the temperatures sensor circuit including a calibration circuit responsive to a temperature coding signal and a temperature sensor. The temperature sensor circuit has a first or test mode state in which a temperature output signal of the temperature sensor circuit is based on a temperature sensor output control signal and a second or normal operating mode state in which the temperature output signal is based on the temperature sensor and the calibration circuit. A clock period controller circuit includes a calibration circuit responsive to a period coding signal. The clock period controller circuit generates a period control signal based on the temperature output signal and the calibration circuit of the clock period controller circuit. A clock generator circuit generates a clock signal based on the period control signal. Integrated circuit memory devices and methods for controlling the refresh period of the memory devices are also provided.

Abstract translation: 提供用于集成电路器件的时钟生成电路，其包括温度传感器电路，温度传感器电路包括响应于温度编码信号的校准电路和温度传感器。 温度传感器电路具有其中温度传感器电路的温度输出信号基于温度传感器输出控制信号的第一或测试模式状态以及其中温度输出信号基于温度的第二或正常操作模式状态 传感器和校准电路。 时钟周期控制器电路包括响应于周期编码信号的校准电路。 时钟周期控制器电路基于温度输出信号和时钟周期控制器电路的校准电路生成周期控制信号。 时钟发生器电路基于周期控制信号产生时钟信号。 还提供了集成电路存储器件和用于控制存储器件的刷新周期的方法。

公开(公告)号：KR1020020044417A

公开(公告)日：2002-06-15

申请号：KR1020000073801

申请日：2000-12-06

Applicant: 삼성전자주식회사

Inventor： 송기환

IPC: H03K19/0175

CPC classification number: G11C7/1078 ,  G11C7/06 ,  G11C7/1084

Abstract: PURPOSE: A data receiver not to be coupled with quick-back noise is provided to prevent it from coupling with input data and a reference voltage due to a quick-back noise by setting a gain of an input section to "1". CONSTITUTION: A first current source(211) is connected between a supply voltage and an output node and is controlled by a bias voltage. A second current source(220) is connected to the supply voltage and is controlled by the bias voltage. A drain of a first transistor(213) is connected to the output node. A source of the transistor(213) is connected to a ground. The transistor(213) is controlled by input data which is connected to a gate thereof. A drain of a first transistor is connected to the complementary output node. A source of the transistor is connected to a ground. The transistor(213) is controlled by a reference signal which is connected to a gate thereof.

Abstract translation: 目的：提供不与快速反馈噪声耦合的数据接收器，通过将输入部分的增益设置为“1”，防止由于快速噪声而与输入数据和参考电压耦合。 构成：第一电流源（211）连接在电源电压和输出节点之间，并由偏置电压控制。 第二电流源（220）连接到电源电压并由偏置电压控制。 第一晶体管（213）的漏极连接到输出节点。 晶体管（213）的源极连接到地。 晶体管（213）由连接到其栅极的输入数据控制。 第一晶体管的漏极连接到互补输出节点。 晶体管的源极连接到地。 晶体管（213）由连接到其栅极的参考信号控制。

公开(公告)号：KR100304691B1

公开(公告)日：2001-09-29

申请号：KR1019980019805

申请日：1998-05-29

Applicant: 삼성전자주식회사

Inventor： 김창현 ,  송기환

IPC: H01L27/085

Abstract: PURPOSE: An output signal generation circuit having a tristate compensation circuit is provided to prevent a change of an output signal to a tristate state by detecting the tristate state. CONSTITUTION: A main circuit(10) receives an analog signal and outputs an output signal of a CMOS level. The main circuit(10) is formed with a differential amplifier(11) for detecting and amplifying a voltage difference between two input signals(PIN1,PIN2) and a buffer(13). The differential amplifier(11) consists of two PMOS transistors(P1,P2) and three NMOS transistors(N1,N2,N3). The buffer portion(13) is formed with three inverters(I1-I3). A tristate compensation circuit(20) receives the output signal of the main circuit(10) and determines whether the output signal is a CMOS level or not. The tristate compensation circuit(20) outputs a control signal to the main circuit(10) if the output signal is not the CMOS level but a tristate level. The tristate compensation circuit(20) is formed with a sensor portion(21), a hold portion(23), and a compensation portion(25).

公开(公告)号：KR1020010037846A

公开(公告)日：2001-05-15

申请号：KR1019990045568

申请日：1999-10-20

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  강대운

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/4847 ,  H01L2924/00

Abstract: PURPOSE: A pad structure having tolerance regarding tension applied to a bonding wire is provided to prevent a pad from being thrown away, by using via holes installed in a direction perpendicular to a progress direction of the bonding wire. CONSTITUTION: A bonding pad(20) is connected to a package pin through a bonding wire(10). A lower conductive layer is formed on a semiconductor substrate. An insulating layer is formed on the conductive layer. Via holes(30) are built in the insulating layer. The via holes have a length corresponding to a side of the bonding pad, installed in a direction that the bonding wire is wired. An upper conductive layer is connected to the lower conductive layer, burying the via holes.

Abstract translation: 目的：通过使用安装在与接合线的行进方向垂直的方向上的通孔，提供对施加到接合线的张力的公差的衬垫结构，以防止衬垫被丢弃。 构成：焊盘（20）通过接合线（10）连接到封装销。 在半导体衬底上形成下导电层。 在导电层上形成绝缘层。 通孔（30）内置在绝缘层中。 所述通孔的长度对应于所述接合焊盘的与所述接合线接合的方向安装的一侧。 上导电层连接到下导电层，埋入通孔。

公开(公告)号：KR1020000034921A

公开(公告)日：2000-06-26

申请号：KR1019990038400

申请日：1999-09-09

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  박찬종

IPC: G11C11/34

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

Abstract: PURPOSE: A packet-type semiconductor memory device is provided to have a current control circuit which obtains a division voltage of a normal state and minimizes a variation of VOH and VOL voltages. CONSTITUTION: A packet-type semiconductor memory device comprises first and second pads (P31,P32), an output driver(O31), a current control circuit(CT31) and a control circuit(L31). The output driver(O31) is connected to drive the second pad(P32), and the control circuit(L31) generates control signals(Q0-Q5) for controlling a current driving capacity of the output driver(O31), based on an enable signal(CNT) and control bits(ICTR0-ICTR5). The control signals(Q0-Q5) are applied to gates of corresponding transistors(N31-N36) of the output driver(O31). The current control circuit(CT31) divides a voltage between the first and second pads(P31,P32) in response to a current control enable signal(CCTG), and compares the divided voltage(Vcmp) with a reference voltage(Vref) to output the control bits(ICTR0-ICTR5). The current control circuit(CT31) contains a first buffer(T31) and a second buffer(T32). The first buffer(T31) serves as a transfer circuit for transferring a voltage(VOH) of the first pad(P31), and directly outputs the voltage(VOH) to an output terminal in response to the current control enable signal(CCTG). The second buffer(T32) serves as a transfer circuit for transferring a voltage(VOL) of the second pad(P32), and directly outputs the voltage(VOL) to an output terminal in response to the current control enable signal(CCTG).

Abstract translation: 目的：提供分组型半导体存储器件以具有获得正常状态的分压的电流控制电路，并使VOH和VOL电压的变化最小化。 构成：分组型半导体存储器件包括第一和第二焊盘（P31，P32），输出驱动器（O31），电流控制电路（CT31）和控制电路（L31）。 输出驱动器（O31）被连接以驱动第二焊盘（P32），并且控制电路（L31）基于使能而产生用于控制输出驱动器（O31）的电流驱动能力的控制信号（Q0-Q5） 信号（CNT）和控制位（ICTR0-ICTR5）。 控制信号（Q0-Q5）被施加到输出驱动器（O31）的相应晶体管（N31-N36）的栅极。 电流控制电路（CT31）响应于电流控制使能信号（CCTG），对第一和第二焊盘（P31，P32）之间的电压进行分压，并将分压电压（Vcmp）与参考电压（Vref）进行比较以输出 控制位（ICTR0-ICTR5）。 电流控制电路（CT31）包含第一缓冲器（T31）和第二缓冲器（T32）。 第一缓冲器（T31）用作传送第一焊盘（P31）的电压（VOH）的传送电路，并且响应于电流控制使能信号（CCTG）将电压（VOH）直接输出到输出端子。 第二缓冲器（T32）用作用于传送第二焊盘（P32）的电压（VOL）的传送电路，并且响应于电流控制使能信号（CCTG）将电压（VOL）直接输出到输出端子。