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公开(公告)号：KR1020000008021A
公开(公告)日：2000-02-07
申请号：KR1019980027664
申请日：1998-07-09
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76835 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76829
Abstract: PURPOSE: A method of forming metal line is provided to minimize the unwanted capacitance between the metal lines. CONSTITUTION: The method of forming metal line comprises the steps of forming first inter layer dielectric layer on wafer having conduction layer, forming photo sensitive polymer pattern including first aperture having first width and revealing the upper surface of the first inter layer dielectric layer, forming second inter layer dielectric layer on the polymer pattern and on the revealed first inter layer dielectric layer, forming mask pattern including second aperture having second width wider than the first width and revealing the second inter layer dielectric layer at the position corresponding to the first aperture on the second inter layer dielectric layer, forming metal line by dry etching the second inter layer dielectric layer with the mask pattern as etching mask, forming via hole by dry etching the first inter layer dielectric layer with the polymer pattern as etching mask.
Abstract translation: 目的：提供形成金属线的方法，以最小化金属线之间的不需要的电容。 构成：形成金属线的方法包括以下步骤：在具有导电层的晶片上形成第一层间电介质层，形成光敏聚合物图案，其包括具有第一宽度的第一孔，并露出第一层间电介质层的上表面，形成第二层 在所述聚合物图案上和所揭示的第一层间介电层上形成层间电介质层，形成包括具有比所述第一宽度宽的第二宽度的第二孔的掩模图案，并且在与所述第一间隔层上的所述第一孔相对应的位置处露出所述第二层间电介质层 第二层间介电层，通过用掩模图案作为蚀刻掩模干蚀刻第二层间电介质层，形成金属线，通过用聚合物图案作为蚀刻掩模干蚀刻第一层间电介质层来形成通孔。
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公开(公告)号：KR1019970018360A
公开(公告)日：1997-04-30
申请号：KR1019950029318
申请日：1995-09-07
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: STI(Shallow Trench Isolation)을 이용한 소자분리 방법이 개시된다. 본 발명은 패드산화막과 질화막 패턴에 의해 활성영역이 정의된 반도체 기판을 식각하여 트렌치 매립을 위한 1차 절연막 증착공정과, 상기 절연막의 일부를 제거하기 위한 식각 공정과, 상기 트렌치 완전 매립을 위한 2차 절연막 증착공정을 포함한다. 본 발명에 의하면, 절연막을 다단계의 증착공정에서 매립(filling)하고 이러한 다단계 매립공정 사이에 습식식각 공정을 추가하는 단순한 공정개선을 통하여, 보이드(voie)없이 트렌치를 매립할 수 있다.
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公开(公告)号：KR1019960019488A
公开(公告)日：1996-06-17
申请号：KR1019940032122
申请日：1994-11-30
Applicant: 삼성전자주식회사
IPC: H01L21/027
Abstract: 반도체장치의 배선패턴 형성방법이 개시되어 있다. 마스크패턴을 사용하여 감광재료층과 제1배선물질층이 적층되어 있는 기판에 대해 포토에칭을 수행하여 제1배선패턴을 형성하되, 상기 마스크패턴의 패턴간격이 상기 제1배선패턴 배선선폭의 3배가 되도록 하는 한편, 상기 포토에칭시 상기 기판을 상기 제1배선물질층이 적층된 두께만큼 과도식각한다. 다음, 상기 과도식각된 결과물 전면에 균일한 두께의 절연막을 형성하고, 상기 절연막의 상부에 제2배선물질층을 적층한 후, 상기 제2배선물질층을 상기 제1배선패턴의 표면이 드러날 때가지 식각 또는 연마하여 제2배선패턴을 형성한다.
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公开(公告)号：KR101369361B1
公开(公告)日：2014-03-04
申请号：KR1020070103709
申请日：2007-10-15
Applicant: 삼성전자주식회사
IPC: H01L21/3205
CPC classification number: H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
Abstract: 크랙의 전달이나 수분의 침투를 차단하는 일체형 크랙 스탑 구조물을 구비한 반도체 장치를 개시한다. 반도체 기판은 활성 영역 및 상기 활성 영역을 둘러싸는 크랙 스탑 영역을 구비한다. 상기 반도체 기판상에 층간 절연막들이 순차 적층된다. 제1듀얼 다마신 패턴들이 층간 절연막들 각각 형성되며, 기판 표면에 대하여 수직하게 상기 활성 영역에 배열되어 상기 기판의 제1부분을 노출시킨다. 제1개구부는 상기 크랙 스탑 영역에 배열되고 상기 층간 절연막들에 걸쳐 형성되어 상기 반도체 기판의 제2부분을 노출시킨다. 제1듀얼 다마신 배선들이 상기 제1듀얼 다마신 패턴들내에 각각 형성되어 상기 기판 표면에 대하여 수직하게 배열되고, 상기 기판의 상기 노출된 제1부분과 콘택된다. 일체형 제1크랙 스탑 구조물이 상기 제1개구부내에 형성되어 상기 기판의 상기 노출된 제2부분과 콘택된다.
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Patent Agency Ranking
公开(公告)号：KR1020100107548A
公开(公告)日：2010-10-06
申请号：KR1020090025658
申请日：2009-03-26
Applicant: 삼성전자주식회사
IPC: H01L21/3205 , H01L21/027 , H01L21/768
CPC classification number: H01L27/10852 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L28/91 , G03F7/70433
Abstract: PURPOSE: A method for forming an insulating film pattern is provided to prevent the generation of bowing due to a deposition process by omitting an additional deposition process for regulating the width of an opening part. CONSTITUTION: An insulating film(102) is formed on a substrate(100). An organic polymer film(104) and a hard mask film are formed on the insulating film. The hard mask film is patterned to form a pre-hard mask pattern including a first opening part(110a). The pre-hard mask pattern is re-patterned to form a hard mask pattern(120) including the first opening part and a second opening part(114a). A spacer for regulating the width of the opening parts is formed on the sidewalls of the first and the second opening parts.
Abstract translation: 目的：提供一种用于形成绝缘膜图案的方法，以通过省略用于调节开口部分的宽度的附加沉积工艺来防止由于沉积工艺而产生弯曲。 构成：在基板（100）上形成绝缘膜（102）。 在绝缘膜上形成有机聚合物膜（104）和硬掩模膜。 图案化硬掩模膜以形成包括第一开口部（110a）的预硬掩模图案。 将预硬掩模图案重新图案化以形成包括第一开口部分和第二开口部分（114a）的硬掩模图案（120）。 用于调节开口部分的宽度的间隔件形成在第一和第二开口部分的侧壁上。
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公开(公告)号：KR1020100088854A
公开(公告)日：2010-08-11
申请号：KR1020090007980
申请日：2009-02-02
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/0847 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L21/02293
Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to maintain a stress which applied to the channel region of a gate structure by forming a trench which includes regions with different depths. CONSTITUTION: A first gate structure(120a) and a second gate structure(120b) are spaced apart on a substrate(100). A source/drain region(110) is formed on both sides of the first and the second gate structures. A trench(130) is formed between the first and the second gate structures. An epitaxial layer(140) fills the trench. A first gate insulating layer(121a) and a second gate insulating layer(121b) electrically insulates the substrate, a first gate electrode(122a), and a second gate electrode(122b). A first sidewall spacer(123a) and a second sidewall spacer(123b) are composed of an insulating material.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过形成包括具有不同深度的区域的沟槽来保持施加到栅极结构的沟道区的应力。 构成：第一栅极结构（120a）和第二栅极结构（120b）在衬底（100）上间隔开。 源极/漏极区域（110）形成在第一和第二栅极结构的两侧。 在第一和第二栅极结构之间形成沟槽（130）。 外延层（140）填充沟槽。 第一栅极绝缘层（121a）和第二栅极绝缘层（121b）使基板，第一栅电极（122a）和第二栅电极（122b）电绝缘。 第一侧壁间隔物（123a）和第二侧壁间隔物（123b）由绝缘材料构成。
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公开(公告)号：KR1020100061034A
公开(公告)日：2010-06-07
申请号：KR1020080119907
申请日：2008-11-28
Applicant: 삼성전자주식회사
IPC: H01L21/308 , H01L21/027
CPC classification number: H01L21/0337 , H01L21/0338
Abstract: PURPOSE: A fabricating method of semiconductor integrated circuit devices are provided to form a spacer layer on a hard mask pattern with conformal by forming a line spacer with a low temperature oxide film. CONSTITUTION: A hard mask layer is formed on a semiconductor substrate(100). A first etching mask including a plurality of first line patterns is formed on the hard mask layer. The hard mask layer is etched and the first hard mask pattern is formed. A second etching mask including a plurality of second line patterns is formed in the first hard mask pattern. The first hard mask pattern is etched to form the second hard mask pattern(122). The spacer(131) is formed in the sidewall of the second hard mask pattern.
Abstract translation: 目的：提供半导体集成电路器件的制造方法，通过形成具有低温氧化膜的线间隔物，在硬掩模图案上形成间隔层。 构成：在半导体衬底（100）上形成硬掩模层。 在硬掩模层上形成包括多个第一线图案的第一蚀刻掩模。 蚀刻硬掩模层并形成第一硬掩模图案。 在第一硬掩模图案中形成包括多个第二线图案的第二蚀刻掩模。 蚀刻第一硬掩模图案以形成第二硬掩模图案（122）。 间隔物（131）形成在第二硬掩模图案的侧壁中。
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公开(公告)号：KR1020080002274A
公开(公告)日：2008-01-04
申请号：KR1020060060990
申请日：2006-06-30
Applicant: 삼성전자주식회사
IPC: H01L21/335
Abstract: A method for forming a semiconductor device with a FET(field effect transistor) transistor is provided to minimize a leakage current between metal silicide and a semiconductor substrate by avoiding an excessive growth of metal silicide. A gate insulation layer(14) and a gate electrode(16) are sequentially stacked on a semiconductor substrate(10). A first insulation layer is formed on the resultant structure. A first etch-back process is performed on the first insulation layer until the upper surface and upper sidewall of the gate electrode are exposed, so that a first spacer(18a) with an exposed surface is formed. A second insulation layer is formed on the resultant structure. A second etch-back process is performed on the second insulation layer to form a second spacer(22a) covering the exposed surface of the first spacer. The process for performing the first etch-back process includes the following steps. A first anisotropic etch process is performed on the first insulation layer until the upper surface of the gate electrode is exposed. A second anisotropic etch process is performed on the firstly anisotropically etched first insulation layer until the upper sidewall of the gate electrode is exposed.
Abstract translation: 提供一种用FET（场效应晶体管）晶体管形成半导体器件的方法，以通过避免金属硅化物的过度生长来最小化金属硅化物与半导体衬底之间的漏电流。 栅极绝缘层（14）和栅电极（16）依次层叠在半导体基板（10）上。 在所得结构上形成第一绝缘层。 在第一绝缘层上进行第一次回蚀处理，直至栅电极的上表面和上侧露出，从而形成具有暴露表面的第一间隔物（18a）。 在所得结构上形成第二绝缘层。 在第二绝缘层上执行第二回蚀工艺以形成覆盖第一间隔物的暴露表面的第二间隔物（22a）。 执行第一回蚀处理的过程包括以下步骤。 在第一绝缘层上执行第一各向异性蚀刻工艺，直到露出栅电极的上表面。 对第一各向异性蚀刻的第一绝缘层执行第二各向异性蚀刻工艺，直到露出栅电极的上侧壁。
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公开(公告)号：KR100772902B1
公开(公告)日：2007-11-05
申请号：KR1020060095117
申请日：2006-09-28
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L21/823412 , H01L21/823807 , H01L27/088 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device and a manufacturing method thereof are provided to improve a contact property of the semiconductor device by partially or globally removing a second stress film from an overlap region between the first and the second stress films. A semiconductor substrate(100) includes first and second transistor regions and a border region. The first transistor region includes a first gate electrode and a first source/drain region. The second transistor region includes a second gate electrode and a second source/drain region. The border region includes a third gate electrode and is arranged on an interface between the first and the second transistor regions. A first stress film(131) covers the first gate and the first source/drain region and at least a portion of the third generates. A second stress film(135) covers the second gate and the second source/drain region and is not overlapped with the first stress film or partially overlapped with the first stress film. A thickness of the partially overlapped second stress film is smaller than that of the second stress film on the second transistor region.
Abstract translation: 提供半导体器件及其制造方法，以通过从第一和第二应力膜之间的重叠区域部分地或全局地去除第二应力膜来改善半导体器件的接触特性。 半导体衬底（100）包括第一和第二晶体管区域和边界区域。 第一晶体管区域包括第一栅极电极和第一源极/漏极区域。 第二晶体管区域包括第二栅极电极和第二源极/漏极区域。 边界区域包括第三栅电极，并且布置在第一和第二晶体管区域之间的界面上。 第一应力膜（131）覆盖第一栅极和第一源极/漏极区域，并且第三应力膜片的至少一部分产生。 第二应力膜（135）覆盖第二栅极和第二源极/漏极区域，并且不与第一应力膜重叠或部分地与第一应力膜重叠。 部分重叠的第二应力膜的厚度小于第二晶体管区域上的第二应力膜的厚度。
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