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1.发明专利
公开(公告)号：KR20210029621A
公开(公告)日：2021-03-16
申请号：KR1020190111084A
申请日：2019-09-06
Applicant: 삼성전자주식회사
CPC classification number: G06F8/65 , G06F11/3612 , G06F8/427 , G06F8/61
Abstract: 본 개시의 다양한 실시예들에 따르면, 전자 장치에 설치된 어플리케이션의 업데이트 시에 런타임 성능(runtime performance)을 향상할 수 있는 장치 및 방법에 관하여 개시한다. 다양한 실시예들에 따른 전자 장치는, 무선 통신을 제공하도록 구성된 통신 회로, 상기 통신 회로와 작동적으로 연결된 적어도 하나의 프로세서, 및 상기 프로세서와 작동적으로 연결된 메모리를 포함하고, 상기 메모리는, 실행 시에, 상기 프로세서가, 어플리케이션의 업데이트를 감지하고, 상기 어플리케이션의 업데이트 감지에 기반하여, 상기 어플리케이션의 업데이트를 위한 업데이트 파일을 획득하고, 상기 어플리케이션에 대한 인스톨(install) 동작에서, 상기 어플리케이션과 관련하여 이전에 기록된 제1 정보와 상기 어플리케이션의 상기 업데이트 파일과 관련된 제2 정보를 획득하고, 상기 제1 정보와 상기 제2 정보의 매칭(matching)에 기반하여, 업데이트 이후에 상기 어플리케이션에서 사용될 새로운 프로파일을 생성하도록 하는 인스트럭션들을 저장할 수 있다. 다양한 실시예들이 가능하다.
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公开(公告)号：KR101807250B1
公开(公告)日：2017-12-11
申请号：KR1020110068507
申请日：2011-07-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/306 , H01L21/31053 , H01L21/31111 , H01L22/12 , H01L22/26 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
Abstract: 3차원반도체장치의제조방법이제공된다. 3차원반도체장치의제조방법은셀 어레이영역및 주변회로영역을포함하는기판을준비하는것; 주변회로영역의기판상에, 주변회로들을포함하는주변구조체를형성하는것; 셀어레이영역의기판을리세스시켜, 주변구조체의상부면보다아래에바닥면을갖는오목부를형성하는것; 오목부가형성된기판을컨포말하게덮으며, 연속적으로적층된복수의박막들을포함하는적층막구조체를형성하되, 적층막구조체는셀 어레이영역상에서최저상면을갖고, 주변회로영역상에서최고상면을갖는것; 적층막구조체를컨포말하게덮는평탄화정지막을형성하는것; 및셀 어레이영역상의평탄화정지막을평탄화종료점으로이용하여적층막구조체를평탄화함으로써, 셀어레이영역과주변회로영역사이에서박막들의상부면들과주변구조체의상부면을동시에노출시키는것을포함한다.
Abstract translation: 提供了一种制造三维半导体器件的方法。 一种制造三维半导体器件的方法包括：准备包括单元阵列区域和外围电路区域的衬底; 在外围电路区域中在衬底上形成包括外围电路的外围结构; 凹进单元阵列区域的衬底以形成凹槽，凹槽具有在外围结构的顶表面下方的底表面; 的凹部被形成为覆盖该衬底共形，以形成层压薄膜结构，其包括多个薄膜依次层叠，在具有最小的顶面，上单元阵列区域的外围电路区域，其具有顶上表面上的层压薄膜结构 。 形成共形地覆盖层压膜结构的平坦停止膜; 通过使用层叠在膜结构的平坦化终点膜，包括那些在单元阵列区和外围电路区之间的同时暴露薄膜结构的衣服的上表面和外周面平坦化mitsel阵列区域平坦化终止。
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公开(公告)号：KR101781621B1
公开(公告)日：2017-09-26
申请号：KR1020100127580
申请日：2010-12-14
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/06 , H01L27/1021 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1658 , H01L45/1683
Abstract: 본발명의기술적사상에따른상변화메모리소자의제조방법은상기기판상에상기하부전극의일부영역을노출시키는컨택홀을포함하는절연막을형성한다. 이어서, 상기컨택홀을채우는상변화물질패턴을형성한다. 다음으로, 상기상변화물질패턴에도펀트(dopant)를도핑한다. 여기서, 상기도펀트는상기상변화물질패턴을구성하는다수의원소들중 상대적으로기화열이높은적어도하나의원소를포함한다.
Abstract translation: 根据本发明的一个方面，提供了一种制造相变存储器件的方法，包括：在器件的衬底上形成绝缘膜，所述绝缘膜包括暴露所述下电极的一部分的接触孔; 随后，形成填充接触孔的相变材料图案。 接下来，相变材料图案掺杂有掺杂剂。 这里，掺杂剂在构成相变材料图案的多个元素中包含具有相对高的汽化热的至少一种元素。
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公开(公告)号：KR101540609B1
公开(公告)日：2015-07-31
申请号：KR1020090015412
申请日：2009-02-24
Applicant: 삼성전자주식회사
IPC: H01L21/3065 , H01L21/027
CPC classification number: H01L21/67069 , H01J37/32642 , H01L21/02087
Abstract: 웨이퍼가과식각되는것을방지하기위한구조를갖는웨이퍼에지식각장치가제공된다. 웨이퍼에지식각장치는, 챔버와, 챔버내부에위치하고웨이퍼가안착되는척과, 웨이퍼와이격되어웨이퍼상부에배치되는플레이트와, 웨이퍼의에지를따라형성되며플레이트외주부에결합되는에지링을포함하되, 에지링은웨이퍼와이격되어평행면을형성하는링 베이스와, 링베이스로부터돌출되어웨이퍼의에지를웨이퍼의중앙부와격리하는제1 링돌기를포함한다
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公开(公告)号：KR1020140024609A
公开(公告)日：2014-03-03
申请号：KR1020120090784
申请日：2012-08-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L23/48 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L27/0688 , H01L2924/00
Abstract: A 3D nonvolatile memory device and a fabricating method thereof are provided. The 3D nonvolatile memory device includes a substrate where a cell array region and a connection region are defined, an electrode structure which is formed on the cell array region and the connection region and includes stacked electrodes, a second recess formed on the electrode structure on the connection region, a first recess which is formed on the electrode structure of the connection region and is arrange between the cell array region and the second recess, and vertical lines which are formed on the upper surface of the electrode exposed by the first recess.
Abstract translation: 提供了一种3D非易失性存储器件及其制造方法。 3D非易失性存储器件包括其中限定了单元阵列区域和连接区域的基板，形成在单元阵列区域和连接区域上并且包括堆叠电极的电极结构，形成在电极结构上的第二凹部 连接区域，形成在连接区域的电极结构上并且布置在电池阵列区域和第二凹部之间的第一凹部以及形成在由第一凹部暴露的电极的上表面上的垂直线。
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Patent Agency Ranking
公开(公告)号：KR1020130096526A
公开(公告)日：2013-08-30
申请号：KR1020120018055
申请日：2012-02-22
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L27/11556 , H01L27/11582 , H01L21/76897 , H01L27/0688
Abstract: PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to improve the reliability of the memory device by including a contact plug and an etch stop layer pattern formed on a common source line strapping region. CONSTITUTION: Channel regions (112) are extended in the vertical direction on a substrate. Gate electrodes (150) are separated in the vertical direction and the horizontal direction along an outer wall of the channel regions. A first impurity region is provided to the substrate and is formed on the lower part of the channel regions. A first interlayer insulating film is formed on the substrate and covers the gate electrodes and the channel regions. A contact hole passes through the first interlayer insulating film and is formed between the adjacent gate electrodes. A contact plug (170) is formed in the contact hole and is electrically connected to a second impurity region. An etch stop layer pattern (182) is formed on the contact plug and the first interlayer insulating film.
Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，通过包括在公共源极线捆扎区域上形成的接触插塞和蚀刻停止层图案来提高存储器件的可靠性。 构成：通道区域（112）在衬底上沿垂直方向延伸。 栅极电极（150）沿着沟道区域的外壁在垂直方向和水平方向上分离。 第一杂质区域设置在衬底上并形成在沟道区域的下部。 第一层间绝缘膜形成在基板上并覆盖栅电极和沟道区。 接触孔穿过第一层间绝缘膜并形成在相邻的栅电极之间。 接触插塞（170）形成在接触孔中并与第二杂质区电连接。 在接触插塞和第一层间绝缘膜上形成蚀刻停止层图案（182）。
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公开(公告)号：KR1020130027823A
公开(公告)日：2013-03-18
申请号：KR1020110091289
申请日：2011-09-08
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11582 , H01L27/11573 , H01L29/7926 , H01L21/28282 , H01L21/28273 , H01L21/31051
Abstract: PURPOSE: A method for manufacturing a vertical memory device is provided to suppress residue due to a height difference in a planarization process for forming a third interlayer dielectric layer by forming a lower mold structure with the same height as a polishing prevention layer after a substrate of a cell region is exposed. CONSTITUTION: A device isolation layer(105) is formed on a substrate(100) which is divided into a first region and a second region. A gate structure(130) is formed in the first region. The gate structure includes a gate insulation layer(110) and a gate electrode(120). A gate spacer(140) is formed on an sidewall of the gate structure. A first interlayer dielectric layer(150) which covers the gate structure and the gate spacer is formed in the first region and the second region of the substrate. A first polishing prevention layer(160) and a second interlayer dielectric layer are successively formed on the first interlayer dielectric layer. A second interlayer dielectric pattern(175) is formed by performing a planarization process on the upper side of the second interlayer dielectric layer. [Reference numerals] (AA) First direction; (BB) Second direction
Abstract translation: 目的：提供一种用于制造垂直存储装置的方法，用于通过在基板上形成具有与抛光防止层相同的高度的下模具结构来抑制用于形成第三层间电介质层的平坦化工艺中的高度差的残留 暴露细胞区域。 构成：在分为第一区域和第二区域的基板（100）上形成器件隔离层（105）。 在第一区域中形成栅极结构（130）。 栅极结构包括栅极绝缘层（110）和栅极电极（120）。 栅极间隔物（140）形成在栅极结构的侧壁上。 在衬底的第一区域和第二区域中形成覆盖栅极结构和栅极间隔物的第一层间电介质层（150）。 在第一层间电介质层上依次形成第一抛光防止层（160）和第二层间电介质层。 通过在第二层间电介质层的上侧进行平坦化处理，形成第二层间电介质图案（175）。 （附图标记）（AA）第一方向; （BB）第二方向
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公开(公告)号：KR1020130027234A
公开(公告)日：2013-03-15
申请号：KR1020110090708
申请日：2011-09-07
Applicant: 삼성전자주식회사
CPC classification number: D06F33/02 , D06F39/08 , D06F39/087 , D06F41/00 , D06F2232/06 , Y02B40/50
Abstract: PURPOSE: A washing machine and a method for controlling the same are provided to improve the solubility and the washing performance of a detergent using a washing plate capable of wobbling washing. CONSTITUTION: A controller detects the amount of laundries inserted into a washing tub when a user selects a washing course(70). The controller sets the water level by the detected amount of the laundries(71). Washing water is supplied to the set water level for conducting a first washing process when the water level is set, and the controller rotates a washing plate(72). The operation of the washing plate stops when the washing water reaches the first set water level, and the washing water is supplied until the water reaches the second set water level(74). The controller stops the water supply when the water reaches the second set water level, and conducts the first washing process(76, 77). The controller stops the first washing process when the first washing time passes the first preset time, and rotates the washing plate while supplying the washing water(79, 80). The water supply is stopped when the washing water reaches the third set water level, and a second washing process is conducted(82, 83). The controller conducts a dehydration process, a rinsing process, and a second dehydration process. [Reference numerals] (70) Detecting the amount of laundries; (71) Setting the level of water; (72,80,86) Supplying water, and rotating a washing plate; (73) Is a first set water level reached?; (74) Stopping the rotation of the washing plate, and supplying water; (75) Is a second set water level reached?; (76,82,88) Stopping the supply of water; (77) Executing a first washing operation; (78) Is a first set time elapsed?; (79) Stopping the first washing operation; (81) Is a third set water level reached?; (83) Executing a second washing operation; (84) Is a second set time elapsed?; (85) Stopping a second washing operation, and dehydrating; (87) Is a rinse set water level reached?; (89) Executing a rinsing operation; (90) Dehydrating; (AA) Start; (BB,DD,FF,HH,JJ,LL) No; (CC,EE,GG,II,KK,MM) Yes; (NN) End
Abstract translation: 目的：提供一种洗衣机及其控制方法，以提高使用能够摆动洗涤的洗涤板的洗涤剂的溶解度和洗涤性能。 构成：当用户选择洗涤过程（70）时，控制器检测插入洗涤桶中的洗衣量。 控制器将水位设定为检测到的洗衣量（71）。 当设定水位时，将洗涤水供给至设定水位进行第一洗涤处理，并且控制器旋转清洗板（72）。 当洗涤水达到第一设定水位时，洗涤板的操作停止，并且供应洗涤水直到水达到第二设定水位（74）。 当水达到第二设定水位时，控制器停止供水，并进行第一次清洗处理（76,77）。 当第一洗涤时间经过第一预设时间时，控制器停止第一洗涤过程，并在提供洗涤水（79,80）的同时旋转洗涤板。 当洗涤水达到第三设定水位时，停止供水，进行第二次清洗处理（82,83）。 控制器进行脱水处理，漂洗处理和第二脱水处理。 （附图标记）（70）检测洗衣液的量; （71）设定水位; （72,80,86）供水，旋转洗板; （73）是否达到第一套水位？ （74）停止洗涤板的旋转，供水; （75）达到第二套水位？ （76,82,88）停止供水; （77）执行第一次洗涤操作; （78）是第一次设定时间吗？ （79）停止第一次洗涤操作; （81）是否达到第三套水位？ （83）执行第二次洗涤操作; （84）第二个设定时间过去了吗？ （85）停止第二次洗涤操作，脱水; （87）是否达到冲洗水位？ （89）执行冲洗操作; （90）脱水; （AA）开始; （BB，DD，FF，HH，JJ，LL）否; （CC，EE，GG，II，KK，MM）是; （NN）结束
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公开(公告)号：KR1020070048819A
公开(公告)日：2007-05-10
申请号：KR1020050105771
申请日：2005-11-07
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: 기판 표면 피트 생성이 억제된 불순물 영역 형성 방법에 있어서, 우선 반도체 기판에 희생 산화막을 형성하고, 상기 희생 산화막으로 불순물을 주입한다. 상기 희생 산화막 상에 생성된 오염물이 확산되어 기판 표면에 부착되는 것을 억제시키고 상기 불순물을 활성화하기 위하여 산소 및 수소 분위기 하에서 상기 반도체 기판을 열처리한다. 이어서, 상기 희생 산화막을 제거한다. 이때, 상기 열처리 시, 수소 및 산소를 주입함으로써 산소 라디칼을 반도체 기판 표면과 반응시킴으로써, 반도체 기판 표면에 피트가 생성되는 것을 미연에 방지할 수 있다.
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10.发明公开
公开(公告)号：KR1020070030022A
公开(公告)日：2007-03-15
申请号：KR1020050084761
申请日：2005-09-12
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L27/10894 , H01L27/10876 , H01L29/4236 , H01L29/66621 , H01L27/10823
Abstract: A structure for a recessed gate electrode is provided to improve the operation characteristic of a cell transistor by controlling the transfer of voids generated in an expanded recess when a recessed cell transistor having a recess whose lower part is expanded is formed. A substrate(100) includes a first recess(104) and a second recess(108) having a broader inner width than that of the first recess such that the second recess is connected to the lower part of the first recess. A gate oxide layer(110) is formed on the upper surface of the substrate and the inner walls of the first and the second recesses. The inside of the first recess is filled with a first polysilicon layer(118) doped with impurities of a first density. The inside of the second recess is filled with a second polysilicon layer(120) doped with impurities of a second density higher than the first density such that the second polysilicon layer includes voids(115) in the center of the second recess. A third polysilicon layer(122) is formed on the gate oxide layer and the first polysilicon layer, having impurities of a third density. The second density included in the second polysilicon layer has a density capable of controlling the position of the void transferred by diffusion of silicon. The impurities doped into the first, second and third polysilicon layers can be the same conductivity type.
Abstract translation: 提供了一种用于凹形栅电极的结构，以便当形成具有其下部扩展的凹部的凹槽单元晶体管时，通过控制在扩展凹部中产生的空隙的转移来改善单元晶体管的操作特性。 基板（100）包括第一凹槽（104）和第二凹槽（108），其具有比第一凹槽更宽的内部宽度，使得第二凹槽连接到第一凹槽的下部。 在基板的上表面和第一和第二凹槽的内壁上形成栅氧化层（110）。 第一凹部的内部填充有掺杂有第一密度的杂质的第一多晶硅层（118）。 第二凹部的内部填充有掺杂高于第一密度的第二密度的杂质的第二多晶硅层（120），使得第二多晶硅层包括位于第二凹槽中心的空隙（115）。 第三多晶硅层（122）形成在具有第三密度的杂质的栅极氧化物层和第一多晶硅层上。 包含在第二多晶硅层中的第二密度具有能够控制由硅的扩散转移的空隙的位置的密度。 掺杂到第一，第二和第三多晶硅层中的杂质可以是相同的导电类型。
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