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公开(公告)号：KR100700967B1
公开(公告)日：2007-03-28
申请号：KR1020050132316
申请日：2005-12-28
Applicant: 전자부품연구원
Abstract: A front end module in a mobile communication device is provided to reduce signal loss due to electric lines and to reduce the volume. A first dielectric layer(301) includes a power amplifier IC and a micro strip line. A second dielectric layer(302) includes a duplexer, an LPF(Low Pass Filter), and an HPF(High Pass Filter). A third dielectric layer(303) includes an upper pattern of a capacitor which suppresses a DC component of a transmission signal and is arranged under the second dielectric layer. A fourth dielectric layer(304) includes a third inductor pattern and a lower pattern of the capacitor for suppressing the DC component from the transmission signal, and is arranged under the third dielectric layer. A fifth dielectric layer(305) includes two shunt capacitors for impedance matching and is arranged under the fourth dielectric layer. Two ground dielectric layers(306,308) include a ground pattern of a transmission line, so that a transmission bandpass filter is duplexed with a reception bandpass filter. A sixth dielectric layer(307) includes ground patterns for the transmission line and the micro strip line. A seventh dielectric layer(309) includes a DC bias RF(Radio Frequency) choke, which is connected to the micro strip line and the shunt capacitor.
Abstract translation: 提供移动通信设备中的前端模块以减少由于电线引起的信号损失并减小体积。 第一电介质层（301）包括功率放大器IC和微带线。 第二介质层（302）包括双工器，LPF（低通滤波器）和HPF（高通滤波器）。 第三电介质层（303）包括电容器的上部图案，其抑制透射信号的DC分量并且布置在第二介电层下方。 第四电介质层（304）包括电容器的第三电感器图案和下部图案，用于抑制来自透射信号的DC分量，并且布置在第三介电层下方。 第五电介质层（305）包括用于阻抗匹配的两个并联电容器，并且布置在第四介电层下方。 两个接地电介质层（306,308）包括传输线的接地图案，使得传输带通滤波器与接收带通滤波器双工。 第六电介质层（307）包括用于传输线和微带线的接地图案。 第七电介质层（309）包括连接到微带线和分流电容器的DC偏压RF（射频）扼流圈。
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公开(公告)号：KR1020060071987A
公开(公告)日：2006-06-27
申请号：KR1020040110507
申请日：2004-12-22
Applicant: 전자부품연구원
IPC: H01L41/273 , H01L41/29
CPC classification number: H01L41/273 , H01L41/083 , H01L41/187 , H01L41/293 , H01L41/312 , H01L41/332
Abstract: 본 발명은 적층 세라믹 소자의 제조 방법에 관한 것으로, 소결(Sintering)된 도전성 페이스트막을 억제층(Constraining layer)으로 이용하여, 적층된 세라믹 기판으로 이루어진 소자 구조물의 XY방향으로 수축을 방지하고, 종래 기술과 같은 연마 공정이 불필요하고, 소자 구조물의 두께를 얇게 할 수 있으며, 정밀한 전극 패턴을 형성할 수 있는 효과가 있다.
소결, 세라믹, 수축, 억제, 패턴-
公开(公告)号：KR100543411B1
公开(公告)日：2006-01-23
申请号：KR1020030040778
申请日：2003-06-23
Applicant: 전자부품연구원
IPC: H01L23/28
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2924/00014
Abstract: 본 발명은 고주파 통신 모듈의 패키징 장치 및 그 제조 방법에 관한 것으로서, 본딩 와이어를 통해 고주파 통신 모듈의 상면에 형성된 패드와 전기적으로 연결되는 패키징 장치의 급전선 하부에 이중의 금속층을 형성함으로써, 이를 통해 병렬 커패시턴스를 형성해 본딩 와이어로 인한 고주파 기생 인덕턴스를 감소시켜 고주파 영역에서의 급전선 전송 특성을 향상시킬 수 있도록 한다.
고주파, 모듈, 패키징, 금속, 단자, 이중층, 급전선-
公开(公告)号：KR100537740B1
公开(公告)日：2005-12-20
申请号：KR1020040001113
申请日：2004-01-08
Applicant: 전자부품연구원
IPC: H03B5/32
Abstract: 본 발명은 유전체기판 적층형 전압제어발진기에 관한 것으로서, 인덕터나, 커패시터 등의 전압 제어 발진기용 단위 소자들이 PCB기판에 칩 부품 형태로 실장되는 종래의 2차원적인 구조와는 달리, 관련 단위 소자들이 유전체 기판, 예컨대 세라믹 시트(sheet)를 적층하고 일체화시켜 3차원적인 구조로 형성함으로써, 종래와 같이 칩부품을 사용하지 않아도 되어 칩부품 비용과 그 실장 비용을 절감할 수 있고, 3차원적으로 모듈을 제조할 수 있어 그 크기를 최소화할 수 있도록 한다.
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公开(公告)号：KR100483332B1
公开(公告)日：2005-04-15
申请号：KR1020030026651
申请日：2003-04-28
Applicant: 전자부품연구원
IPC: H01L21/60
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2924/16152 , H01L2924/00014
Abstract: 본 발명은 고주파 통신 모듈의 패키징 장치 및 그 제조 방법에 관한 것으로서, 본딩 와이어를 통해 고주파 통신 모듈의 상면에 형성된 패드와 전기적으로 연결되는 패키징 장치의 급전선 하부에 상호 이격된 한 쌍의 금속 단자를 형성하여 본딩 와이어로 인한 고주파 기생 인덕턴스를 커패시턴스의 임피던스 매칭으로 감소시켜 고주파 영역에서 급전선의 전송 특성을 향상시킬 수 있도록 한다.
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Patent Agency Ranking
公开(公告)号：KR1020050000183A
公开(公告)日：2005-01-03
申请号：KR1020030040778
申请日：2003-06-23
Applicant: 전자부품연구원
IPC: H01L23/28
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2924/00014
Abstract: PURPOSE: A packaging device of a high frequency communication module and a manufacturing method thereof are provided to reduce high frequency parasitic inductance caused by a bonding wire by forming parallel capacitance using a double metal film structure under a feeding line. CONSTITUTION: A first sheet structure(13) with a pair of first metal terminals(12) is provided. A second sheet structure(23) with a pair of second metal terminals(22) is formed on the first sheet structure. A third sheet structure(33) with a feeding line(32) is formed on the second sheet structure. At this time, a double metal film structure made of the first and second metal terminals is completed under the feeding line. A fourth sheet structure(43) is formed on the third sheet structure. The first to fourth sheet structure are ceramic green sheets.
Abstract translation: 目的：提供一种高频通信模块的封装装置及其制造方法，以通过在馈电线路下使用双金属膜结构形成并联电容来降低由接合线引起的高频寄生电感。 构成：提供具有一对第一金属端子（12）的第一片状结构（13）。 具有一对第二金属端子（22）的第二片状结构（23）形成在第一片状结构上。 具有馈电线（32）的第三片结构（33）形成在第二片结构上。 此时，在馈电线下完成由第一和第二金属端子制成的双金属膜结构。 在第三片结构上形成第四片结构（43）。 第一至第四片结构是陶瓷生片。
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公开(公告)号：KR1020040095379A
公开(公告)日：2004-11-15
申请号：KR1020030026651
申请日：2003-04-28
Applicant: 전자부품연구원
IPC: H01L21/60
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2924/16152 , H01L2924/00014
Abstract: PURPOSE: A packaging apparatus of an RF communication module and a fabricating method thereof are provided to improve a transmitting characteristic of a feeding line within an RF band by reducing RF parasitic capacitance due to a bonding wire. CONSTITUTION: The first sheet structure(23) is fabricated by forming the first cavity(21) on a predetermined region of the first sheet, printing a couple of metal terminals(22) on both sides of the first cavity, and forming a ground side on a bottom face of the first sheet. The second sheet structure(33) is fabricating by forming the second cavity(31) on the predetermined region of the second sheet and printing a feeding line on both sides of the second cavity. The third sheet structure(43) is fabricated by forming the third cavity on the predetermined region of the third sheet and forming the fourth cavity on both sides of the third cavity. The first to the third structures are formed with one body. The ground side of the first sheet is bonded to a plated metal body.
Abstract translation: 目的：提供RF通信模块的包装装置及其制造方法，通过降低由于接合线引起的RF寄生电容来提高RF频带内的馈线的发送特性。 构成：第一片结构（23）通过在第一片的预定区域上形成第一空腔（21），在第一腔的两侧印刷一对金属端子（22）并形成接地侧 在第一张纸的底面上。 第二片结构（33）通过在第二片的预定区域上形成第二腔（31）并在第二腔的两侧上印刷馈送线来制造。 第三片结构（43）通过在第三片的预定区域上形成第三腔并在第三腔的两侧形成第四腔来制造。 第一至第三结构形成一体。 第一片的接地侧与镀金属体接合。
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公开(公告)号：KR1020030004474A
公开(公告)日：2003-01-15
申请号：KR1020010039967
申请日：2001-07-05
Applicant: 전자부품연구원
IPC: G01R27/28
Abstract: PURPOSE: A device for calibrating stack elements, a method for manufacturing the same and a method for measuring a high frequency characteristics by using the same are provided to eliminate the effect of a via hole and accurately measure a high frequency characteristic by making the structure which is similar to an object to be measured. CONSTITUTION: A device(300) for calibrating stack elements includes an impedance pattern layer located at the same height of an incorporated device to be measured and printed thereon an impedance pattern(310) to performing the calibration of the incorporated device, a via hole layer stacked on the impedance pattern layer and having the same height of a via hole(320) of the incorporated device and a plurality of conductive pads(330) stacked on the via hole layer and connected to the impedance pattern(310) through the via hole(320), wherein the device(300) is calibrated to the impedance pattern(310) corresponding to the position of the incorporated device by contacting a measurement device to perform the calibration at the conductive pads(330).
Abstract translation: 目的：提供一种用于校准堆叠元件的装置，其制造方法以及通过使用它们来测量高频特性的方法，以消除通孔的影响并精确地测量高频特性， 类似于要测量的对象。 构成：用于校准堆叠元件的装置（300）包括阻抗图案层，该阻抗图案层位于被测量的并入装置的相同高度并在其上印刷有阻抗图案（310），以执行所结合的装置的校准，通孔层 堆叠在阻抗图案层上并且具有与所结合的器件的通孔（320）相同的高度和堆叠在通孔层上并通过通孔连接到阻抗图案（310）的多个导电焊盘（330） （320），其中通过接触测量装置在所述导电焊盘（330）处执行所述校准，所述装置（300）被校准为对应于所结合的装置的位置的所述阻抗图案（310）。
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公开(公告)号：KR100328882B1
公开(公告)日：2002-08-28
申请号：KR1019980046548
申请日：1998-10-31
Applicant: 전자부품연구원
IPC: H03H9/64
Abstract: 표면 탄성파 듀플렉서 패키지에서, 송신 필터칩 및 수신 필터칩이 장착되어 있는 기판상에 위상 정합용 스트립 라인이 형성되어 있다. 위상 정합용 스트립 라인은 송신 필터칩과 수신 필터칩에 연결되어 수신 필터칩의 위상을 정합시켜 송신주파수 대역의 임피던스를 증가 시킨다. 이와 같이 위상 정합용 스트립 라인이 필터칩과 동일한 기판상에 형성됨에 따라, 구조가 간단해지고 제조 단가가 감소된다.
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公开(公告)号：KR1020020065261A
公开(公告)日：2002-08-13
申请号：KR1020010005690
申请日：2001-02-06
Applicant: 전자부품연구원
IPC: H05K3/40
CPC classification number: H05K3/4629 , H05K1/0306 , H05K1/115 , H05K3/429
Abstract: PURPOSE: A ceramic layered part and a manufacturing method thereof are provided to simplify manufacture process and improve reliability of side terminals of the ceramic layered part. CONSTITUTION: A ceramic layered part comprises ceramic tapes(20), circuit patterns(23) and many plugs(22,26). The ceramic tapes(20) include via holes for connecting the circuit patterns(23) and via holes for side terminals. The plugs(22,26) are formed by filling the via holes with conductive paste. The viscosity of the conductive paste is more than 100,000 cps. The circuit patterns(23) are printed on the ceramic tapes(20). The circuit patterns(23) are overlapped with the plugs(26) for ensuring their connectivity. The ceramic tapes(20) having the plugs(22,26) and the circuit patterns(23) are layered so as to accurate align the plugs(22,26) and the circuit patterns(23) between the ceramic tapes(20). The layered ceramic tapes(20) are cut as dividing the plug(26) into two parts.
Abstract translation: 目的：提供一种陶瓷分层部件及其制造方法，以简化制造工艺，提高陶瓷层叠部件的侧端子的可靠性。 构成：陶瓷分层部分包括陶瓷带（20），电路图案（23）和许多插头（22,26）。 陶瓷带（20）包括用于连接电路图案（23）的通孔和用于侧端子的通孔。 通过用导电浆填充通孔来形成插头（22,26）。 导电糊的粘度大于100,000cps。 电路图案（23）印刷在陶瓷带（20）上。 电路图案（23）与插头（26）重叠以确保它们的连接。 具有插头（22,26）和电路图案（23）的陶瓷带（20）被层叠以便精确地对准陶瓷带（20）之间的插头（22,26）和电路图案（23）。 切割分层陶瓷带（20），将塞子（26）分成两部分。
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