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41.发明公开
公开(公告)号：KR1020050060861A
公开(公告)日：2005-06-22
申请号：KR1020030092589
申请日：2003-12-17
Applicant: 한국전자통신연구원
IPC: G06F9/45
CPC classification number: G06F17/5045 , G06F8/40
Abstract: Provided is a method of generating a dependency specification file of a soft IP comprising, extracting constituent element information by parsing a netlist file of a soft IP and designating an instance name and a component name to input and output ports and function blocks which are constituent elements existing in the soft IP, converting the constituent element information to a vertex for each constituent element, indicating a dependency specification between the vertexes for the respective constituent elements, and generating a dependency specification file by converting the vertexes for the respective constituent elements and the dependency specification that the netlist file of the soft IP contains to an electronic circuit design language file, and outputting the dependency specification file.
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公开(公告)号：KR100491052B1
公开(公告)日：2005-05-24
申请号：KR1020020074418
申请日：2002-11-27
Applicant: 한국전자통신연구원
IPC: G11C29/00
Abstract: 본 발명은 SoC(System on Chip)의 내부 회로, 메모리 및 IP를 시험하기 위한 SoC 시험 회로는 상기 내부 회로로부터의 출력 신호를 입력하고 외부로부터의 스캔 신호 및 스캔 데이터를 입력하여 상기 스캔 신호에 따라 상기 내부 회로로부터의 출력 신호 또는 상기 스캔 데이터 입력을 상기 메모리로 입력시키고 상기 내부 회로로 재입력시키기 위한 입력 데이터 발생 수단과 스트로브 입력, 제 1 및 제 2 선택 입력에 따라 상기 메모리의 출력, 상기 IP의 출력 및 상기 입력 데이터 발생 수단의 출력을 각각 선택하여 다수의 출력 데이터를 출력하기 위한 출력 데이터 발생부를 포함하여 이루어진 것을 특징으로 하고, 상기 SoC 시험 회로를 이용한 SoC 시험 방법은 상기 스캔 데이터 입력으로 0 또는 1을 입력하여 메모리에 데이터를 쓰고 읽어 고착형 불량을 검출하고, 상기 스캔 데이터 입력을 1에서 0으로 또는 0에서 1로 변화시켜 메모리에 데이터를 쓰고 읽어 천이불량 및 유도성 불량을 검출하는 것을 특징으로 하는 SoC 시험 회로 및 시험 방법이 제시된다.
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公开(公告)号：KR100456511B1
公开(公告)日：2004-11-10
申请号：KR1020020077597
申请日：2002-12-07
Applicant: 한국전자통신연구원
IPC: G06F17/50
Abstract: PURPOSE: A device and a method for searching out an IP(Intellectual Property) function of a semiconductor are provided to perform the SOC(System On Chip) design quickly or in a proper time by automatically searching out the function from the semiconductor IP receiving for designing the SOC. CONSTITUTION: A design data input part(100) receives a data sheet and an HDL(Hypertext Delivery Language) code of the semiconductor IP, and corrects an error if a non-identical part is searched out by comparing the data sheet and the HDL code with each format. A function searcher(120) matches a function sentence and a comment for the same function as a pair by searching out each sentence of the data sheet and comparing the sentence with the comment including a waveform extracted from the HDL code. A function sentence storage(140) and a function waveform storage(160) respectively store the function sentence and the waveform received from the function searcher. A function sentence display part(180) and a function waveform sentence display part(200) display the semiconductor IP function by including at least function sentence from the function sentence and the matched waveform.
Abstract translation: 目的：提供一种用于搜索半导体的IP（知识产权）功能的设备和方法，以通过自动搜索来自半导体IP接收的功能来快速或在适当的时间执行SOC（片上系统）设计 设计SOC。 构成：设计数据输入部分（100）接收半导体IP的数据表和HDL（超文本输出语言）代码，并且如果通过比较数据表和HDL代码搜索到不同的部分，则纠正错误 与每种格式。 功能搜索器（120）通过搜索数据表的每个句子并将该句子与包括从HDL代码提取的波形的评论进行比较，来针对作为一对的相同功能的功能句子和评论进行匹配。 功能语句存储器（140）和功能波形存储器（160）分别存储从功能搜索器接收到的功能语句和波形。 功能语句显示部分（180）和功能波形语句显示部分（200）通过至少包括来自功能语句和匹配波形的功能语句来显示半导体IP功能。
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公开(公告)号：KR1020040056997A
公开(公告)日：2004-07-01
申请号：KR1020020083748
申请日：2002-12-24
Applicant: 한국전자통신연구원
IPC: H03B5/04
CPC classification number: H03L1/026
Abstract: PURPOSE: A method for compensating temperature of a crystal oscillator is provided to reduce a pre-decoding logic area, an internal connection logic area, and a cell area as well as a silicon area by reducing a cell number of a capacitor array. CONSTITUTION: A memory address for storing capacitor array address information is calculated by subtracting a temperature offset code from a present temperature level(S14). Data of the memory address are read by using the remaining bits except for the lowest bit as the memory addresses when the lowest bit of the memory address is 0. An average value of the data of the memory address except for the lowest bit and the data of the memory address is increased as much as 1 when the lowest bit of the memory address is 1(S20). The data of the memory address and the average value data are transmitted to the first bank and the second bank by comparing the memory address with the temperature boundary code. A capacitor array is controlled by using the transmitted data.
Abstract translation: 目的：提供一种用于补偿晶体振荡器的温度的方法，通过减小电容器阵列的单元数来减少预解码逻辑区域，内部连接逻辑区域，单元区域以及硅区域。 构成：通过从当前温度水平减去温度偏移代码来计算用于存储电容器阵列地址信息的存储器地址（S14）。 当存储器地址的最低位为0时，通过使用除了最低位之外的剩余位作为存储器地址来读取存储器地址的数据。除最低位之外的存储器地址的数据的平均值和数据 当存储器地址的最低位为1时，存储器地址的增加高达1（S20）。 存储器地址和平均值数据的数据通过将存储器地址与温度边界代码进行比较来发送到第一存储体和第二存储体。 通过使用发送的数据来控制电容器阵列。
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公开(公告)号：KR1020040054409A
公开(公告)日：2004-06-25
申请号：KR1020020081444
申请日：2002-12-18
Applicant: 한국전자통신연구원
IPC: H04J11/00
CPC classification number: H04L27/2657 , H04L27/2676
Abstract: PURPOSE: A frequency offset compensation unit for predicting a variation and a compensating method thereof are provided to minimize power consumption of frequency offset compensation blocks by minimizing a remaining offset accumulation to symbols between estimation periods. CONSTITUTION: An offset estimation unit(510) receives a signal from a communication system according to an estimation period and an estimation algorithm and estimates a normalized frequency offset to a sub-carrier. A feedback controller(511) outputs a compensation value by considering the variation of the frequency offset according to the estimated offset value, the estimation period, and the delay time. An offset compensation signal output unit outputs an offset compensation signal including a sine wave and a cosine wave by using the compensation value of the feedback controller(511). A PLL is used for shifting a phase of an input signal by corresponding offset in order to correct the phase of the input signal to a symbol.
Abstract translation: 目的：提供一种用于预测变化及其补偿方法的频率偏移补偿单元，以通过最小化在估计周期之间的符号的剩余偏移累积来最小化频偏补偿块的功率消耗。 构成：偏移估计单元（510）根据估计周期和估计算法接收来自通信系统的信号，并估计到子载波的归一化频率偏移。 反馈控制器（511）通过根据估计的偏移值，估计周期和延迟时间考虑频率偏移的变化来输出补偿值。 偏移补偿信号输出单元通过使用反馈控制器（511）的补偿值来输出包括正弦波和余弦波的偏移补偿信号。 PLL用于将输入信号的相位移位相应的偏移量，以将输入信号的相位校正为符号。
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Patent Agency Ranking
公开(公告)号：KR1020030053281A
公开(公告)日：2003-06-28
申请号：KR1020010083457
申请日：2001-12-22
Applicant: 한국전자통신연구원
IPC: H03H17/02
CPC classification number: H03H17/02 , H03H17/0269 , H03H17/0444 , H03H17/0671
Abstract: PURPOSE: An interpolation filter using an over-sampling method is provided to control an over-sampling ratio and perform accurately a sampling conversion process by using a two-level interpolation filter and the second order demodulator. CONSTITUTION: An interpolation filter includes a two-level interpolation filter and the second order sigma delta demodulator(300). The two-level interpolation filter is formed with an FIR filter(100) and a Comb filter(200) in order to perform an over-sampling process for a digital input signal of low frequency. The second order sigma delta demodulator receives the sampled signal from the two-level interpolation filter and output PDM data of 1 bit. The FIR filter includes a data register having a shift register, a coefficient ROM for storing filter calculation coefficients, a multiplier for multiplying the output of the data register by the filter coefficient of the coefficient ROM, an adder for adding an output of the multiplier to an output of the accumulator, a multiplexer for receiving the output of the accumulator and outputting parallel data of 10 bits, and a serial/parallel register for converting the parallel data of 10 bits to the serial data of 10 bits.
Abstract translation: 目的：提供使用过采样方法的内插滤波器来控制过采样率，并通过使用二级内插滤波器和二阶解调器来精确地执行采样转换处理。 构成：内插滤波器包括一个二电平内插滤波器和二阶Σ-Δ解调器（300）。 两级内插滤波器由FIR滤波器（100）和梳状滤波器（200）形成，以对低频的数字输入信号执行过采样处理。 二阶Σ-Δ解调器从二电平内插滤波器接收采样信号并输出1位的PDM数据。 FIR滤波器包括具有移位寄存器的数据寄存器，用于存储滤波器计算系数的系数ROM，用于将数据寄存器的输出乘以系数ROM的滤波器系数的乘法器，用于将乘法器的输出相加的加法器 累加器的输出，用于接收累加器的输出并输出10位的并行数据的多路复用器，以及用于将10位的并行数据转换为10位的串行数据的串行/并行寄存器。
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公开(公告)号：KR1020010064243A
公开(公告)日：2001-07-09
申请号：KR1019990062393
申请日：1999-12-27
Applicant: 한국전자통신연구원
IPC: G11C29/00
Abstract: PURPOSE: A latch and memory testing circuit is provided to detects latch and memory malfunctions and to detect various malfunction by using effective testing patterns. CONSTITUTION: The latch and memory testing circuit includes a test pattern generator(105), a data temporary input member(101), a data temporary output member(104), the first data comparator(106), the second data comparator(108) and a clock blocker. The test pattern generator(105) generates test patterns. The data temporary input member(101) buffers the data input from the test pattern generator(105). The data temporary output member(104) buffers the data output from the memory cell. The first data comparator(106) compares the input data with the output data and determines the malfunction of the memory cell. The second data comparator(108) compares the input data with the output data and determines the malfunction of the latch. The clock blocker terminates clock generating when malfunction occurs in the memory cell and the latch.
Abstract translation: 目的：提供锁存和存储器测试电路以检测锁存和存储器故障，并通过使用有效的测试模式来检测各种故障。 构成：锁存和存储器测试电路包括测试码型发生器（105），数据临时输入元件（101），数据临时输出元件（104），第一数据比较器（106），第二数据比较器（108） 和时钟阻滞器。 测试模式发生器（105）产生测试模式。 数据临时输入构件（101）缓冲从测试图案发生器（105）输入的数据。 数据临时输出构件（104）缓冲从存储单元输出的数据。 第一数据比较器（106）将输入数据与输出数据进行比较，并确定存储单元的故障。 第二数据比较器（108）将输入数据与输出数据进行比较，并确定锁存器的故障。 当存储器单元和锁存器发生故障时，时钟阻断器终止时钟产生。
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公开(公告)号：KR100289063B1
公开(公告)日：2001-05-02
申请号：KR1019970069549
申请日：1997-12-17
Applicant: 한국전자통신연구원
Abstract: PURPOSE: An automatic antenna is provided to achieve an improved use convenience by extending antenna through a simple switch pressing action, while reducing the size of telephone adopting such antenna. CONSTITUTION: An automatic antenna comprises a first stage antenna unit(220), a second stage antenna unit(210) and a locking element(230). The first stage antenna unit is formed of a conductive material, and has the locking element for restricting extracting and extending action of the second stage antenna unit. The second stage antenna unit disposed within the first stage antenna unit, includes a spring(215) arranged in the lower portion of the second stage antenna unit, guide rings(212,214) for permitting smooth sliding of antenna, and a stopper(213) arranged in the intermediate portion of the second stage antenna so as to be caught at the locking element of the first stage antenna when a top(211) of the antenna is pressed. The locking element includes a slide type locking vane(231) having a through hole for catching or releasing the second stage antenna unit; a catching semi-circular portion formed at the front portion of the through hole; a releasing semi-circular portion formed at the rear portion of the through hole; and a press-button switch(237) arranged in rear of the slide type locking vane, and which is coupled with a spring(238) and protruded outward.
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公开(公告)号：KR100269253B1
公开(公告)日：2000-10-16
申请号：KR1019980018523
申请日：1998-05-22
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A push type automatic extendable antenna for a portable phone is provided to reduce an outer size of a portable phone by pushing a tip portion of an antenna with one finger and making the antenna being extended up by a spring force. CONSTITUTION: A push type automatic extendable antenna is installed on a side of a portable phone to be extended and retracted. The push type automatic extendable antenna is formed of a conductive material of a tube shape. An antenna bar(210) includes retaining rings(211,213) on an upper part and a lower part thereof to smoothly retract and extend the antenna by supporting springs(221,223). An upper and lower guide(230) permits an extending and retracting to be performed by turns when the upper part of the antenna bar(210) is pressed. A rotational latch body(240) and outer bodies(250,260) are inserted into the antenna bar(210). An upper part spring(221) is installed on an upper end of the antenna bar(210) to transfer a power to the rotational latch part(240) and acts as a shock absorber when the antenna is extended up. An extending spring(223) has a motive power so as for the antenna bar to be extended.
Abstract translation: 目的：提供一种用于便携式电话的推式自动可伸缩天线，以通过用一根手指推动天线的尖端部分并通过弹簧力使天线向上延伸来减小便携式电话的外部尺寸。 构成：推式自动伸缩天线安装在便携式电话的一侧以进行伸缩。 推式自动延伸天线由管状的导电材料形成。 天线杆（210）在其上部和下部包括保持环（211,213），以通过支撑弹簧（221,223）平滑地缩回和延伸天线。 当天线杆（210）的上部被按压时，上部和下部引导件（230）允许轮流执行延伸和缩回。 旋转锁定体（240）和外部本体（250,260）插入到天线杆（210）中。 上部弹簧（221）安装在天线杆（210）的上端，以将电力传递到旋转闩锁部分（240），并且当天线向上延伸时用作减震器。 延伸弹簧（223）具有使天线杆伸长的动力。
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公开(公告)号：KR100243405B1
公开(公告)日：2000-02-01
申请号：KR1019970069572
申请日：1997-12-17
Applicant: 한국전자통신연구원
IPC: H04N17/00
Abstract: 본 발명은 무선으로 송수신되는 패턴 발생장치에 관한 것으로서, 본 발명에서 제공하는 패턴 발생장치는 상기 패턴 발생장치의 표시부로 데이터를 입출력하는 패턴 발생 장치 자체 입출력 수단과, 여러 가지 패턴들을 국제 규격에 맞추어 각 패턴에 해당하는 주파수의 형태로 각종 패턴들을 생성시켜 주는 패턴 발생 제어 수단과, 상기 TV 수상기나 컴퓨터 모니터와 무선 송수신을 수행하는 무선 입출력 인터페이스 수단과, 상기 TV 수상기나 컴퓨터 모니터로부터 수신된 정보를 분석하여 고장 여부 및 고장의 정도를 진단하여 그 결과를 알려주는 고장 진단 수단과, 상기 패턴 발생 장치 자체 입출력 수단과, 패턴 발생 제어 수단과, 무선 입출력 인터페이스 수단 및 고장 진단 수단의 처리를 제어하는 장치 전체 제어 수단과, 상기 TV 수상기나 컴퓨터 모니� � 측에 연결되어 패턴 발생 장치에서 보내준 패턴 정보를 수상기 쪽으로 정확하게 전달시켜주고, 상기 TV 수상기나 컴퓨터 모니터의 상태를 나타내는 정보를 패턴 발생 장치 쪽으로 전송하는 무선 송수신 수단으로 구성되어, 이동에 편리하며, 수상기 고장의 진단과 아울러 그 처방까지 보여주도록 함으로써 미숙련 기술자이더라도 고장에 대한 적절한 조치를 취할 수 있는 장점이 있다.
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