公开(公告)号：KR1020050006304A

公开(公告)日：2005-01-17

申请号：KR1020030045987

申请日：2003-07-08

Applicant: 한국전자통신연구원

Inventor： 박용우 ,  손영준 ,  백문철 ,  서동우 ,  류호준 ,  표현봉

IPC: G02B6/28

CPC classification number: G02B6/34 ,  G02B6/122 ,  G02B6/124

Abstract: PURPOSE: A high efficiency optical coupler by using a leakage mode is provided to manufacture an optical coupler having a high coupling efficiency by using a relatively simple process. CONSTITUTION: A high efficiency optical coupler by using a leakage mode includes a substrate(61), a first core layer(62a), a second core layer(62b), a first clad layer(63), a second clad layer(64) and a Fresnel lens(69). The substrate has a first refractive index(n1). The first core layer having a second refractive index(n2) is formed on the substrate. The second core layer having a third refractive index(n3) is formed on top of the first core layer with spacing from the first core layer by a distance(d). The first clad layer having a fourth refractive index(n4) is placed on the second core layer. The second clad layer is inserted between the first core layer and the second core layer. And, the Fresnel lens is formed on the second clad layer.

Abstract translation: 目的：通过使用泄漏模式提供高效光耦合器，通过使用相对简单的工艺制造具有高耦合效率的光耦合器。 构成：通过使用泄漏模式的高效率光耦合器包括基板（61），第一芯层（62a），第二芯层（62b），第一覆盖层（63），第二覆盖层（64） 和菲涅尔透镜（69）。 基板具有第一折射率（n1）。 在基板上形成具有第二折射率（n2）的第一芯层。 具有第三折射率（n3）的第二芯层形成在第一芯层的顶部上，与第一芯层间隔距离（d）。 具有第四折射率（n4）的第一覆盖层被放置在第二芯层上。 第二覆层被插入在第一芯层和第二芯层之间。 并且，菲涅尔透镜形成在第二覆盖层上。

公开(公告)号：KR1020030037356A

公开(公告)日：2003-05-14

申请号：KR1020010067863

申请日：2001-11-01

Applicant: 한국전자통신연구원

Inventor： 심규환 ,  김상훈 ,  이승윤 ,  박찬우 ,  서동우 ,  강진영

IPC: H01L21/328

Abstract: PURPOSE: A method for manufacturing a heterostructure bipolar transistor is provided to improve electrical characteristics by forming a junction between a thick base and an emitter using self-alignment, and isolating the base using an oxide layer. CONSTITUTION: After sequentially forming a collector(44) and a collector epitaxial layer(46) on a silicon substrate(41), the collector epitaxial layer(46) is isolated by forming an isolation layer(47) on the isolation region of the substrate. After forming a single crystal silicon epitaxial layer having the thickness of 50-200 nm on the resultant structure, an outer base region is defined by oxidizing the predetermined portion of the single crystal silicon epitaxial layer. After forming a base epitaxial layer and a dielectric layer(55), the base epitaxial layer is exposed by etching the dielectric layer(55). After sequentially forming a polysilicon layer and a silicon nitride layer, an emitter(56) made of the polysilicon layer is formed on the exposed base epitaxial layer by patterning the silicon nitride layer, the polysilicon layer and the dielectric layer(55). An outer base(58) and a base(530) are defined by implanting ions into the base epitaxial layer and the single crystal silicon epitaxial layer using the emitter(56) as a mask.

Abstract translation: 目的：提供一种用于制造异质结双极晶体管的方法，以通过使用自对准在厚基极和发射极之间形成结而改善电特性，并使用氧化物层隔离基极。 构成：在硅衬底（41）上依次形成集电极（44）和集电极外延层（46）之后，通过在衬底的隔离区域上形成隔离层（47）来隔离集电极外延层（46） 。 在所得结构上形成厚度为50-200nm的单晶硅外延层之后，通过氧化单晶硅外延层的预定部分来限定外部基极区域。 在形成基极外延层和电介质层（55）之后，通过蚀刻介电层（55）来暴露基极外延层。 在顺序地形成多晶硅层和氮化硅层之后，通过图案化氮化硅层，多晶硅层和电介质层（55），在暴露的基极外延层上形成由多晶硅层制成的发射极（56）。 通过使用发射器（56）作为掩模将离子注入基底外延层和单晶硅外延层来限定外基部（58）和基底（530）。

公开(公告)号：KR1020030017746A

公开(公告)日：2003-03-04

申请号：KR1020010050742

申请日：2001-08-22

Applicant: 한국전자통신연구원

Inventor： 서동우 ,  민봉기 ,  강진영

IPC: H01L27/04

CPC classification number: H01F17/0013 ,  H01F17/0006 ,  H01F27/34

Abstract: PURPOSE: A spiral inductor of a parallel branch structure is provided to increase total inductance by generating mutual inductance between lower metal lines and mutual inductance between an upper metal line and a lower metal line. CONSTITUTION: A spiral inductor(500) includes a lower metal line(510) and an upper metal line(520). The lower metal line(510) and the upper metal line(520) are isolated each other by an insulating layer. The lower metal line(510) and the upper metal line(520) are isolated each other by using a via contact(530). The upper metal line(520) is formed spirally. The lower metal line(510) includes the first and the second lower metal lines(511,512). The first lower metal lines(511) are parallel to each other. The second lower metal lines(512) are parallel to the upper metal line(520).

Abstract translation: 目的：提供并联支路结构的螺旋电感，通过在下金属线之间产生互感和上金属线与下金属线之间的互感来增加总电感。 构成：螺旋电感器（500）包括下金属线（510）和上金属线（520）。 下金属线（510）和上金属线（520）通过绝缘层彼此隔离。 下金属线（510）和上金属线（520）通过使用通孔触点（530）彼此隔离。 上部金属线（520）螺旋形成。 下金属线（510）包括第一和第二下金属线（511,512）。 第一下部金属线（511）彼此平行。 第二下金属线（512）平行于上金属线（520）。

公开(公告)号：KR1020150116384A

公开(公告)日：2015-10-15

申请号：KR1020150018042

申请日：2015-02-05

Applicant: 한국전자통신연구원

Inventor： 임정욱 ,  서동우 ,  윤선진

IPC: H01L31/0468 ,  H01L31/0224

CPC classification number: Y02E10/50

Abstract: 본발명의실시예에따른투명태양전지는기판, 상기기판상에배치된제 1 투명전극, 상기제 1 투명전극상에배치된광 흡수층, 상기광 흡수층상에배치된다중변색층, 및상기다중변색층상에배치된제 2 투명전극을포함하되, 광은상기기판으로입사되고, 입사된광의적어도일부는상기광흡수층에서전류로변환되어상기다중변색층에열을제공할수 있다.

Abstract translation: 根据本发明的实施例，透明太阳能电池包括：基板; 布置在所述基板上的第一透明电极; 布置在所述第一透明电极上的光吸收层; 布置在所述光吸收层上的多色变化层; 以及设置在多色变换层上的第二透明电极。 光入射到衬底上，并且入射光的至少一部分被转换成光吸收层中的电流，以向多色变化层提供热量。

公开(公告)号：KR101287196B1

公开(公告)日：2013-07-16

申请号：KR1020090119308

申请日：2009-12-03

Applicant: 한국전자통신연구원

Inventor： 김상훈 ,  김경옥 ,  김인규 ,  서동우 ,  주지호 ,  장기석

IPC: G02B6/12 ,  H01L31/02

CPC classification number: G02B6/12004 ,  G02B2006/12176 ,  G02B2006/12188 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

Abstract: 광 검출기의 제조방법 및 이에 의해 형성된 광 검출기를 제공한다. 이 광 검출기의 제조방법은, 제1 단결정 반도체층 및 제1 단결정 반도체층으로부터 돌출된 광 도파로를 형성하는 것, 제1 단결정 반도체층 상에 광 도파로를 덮는 절연막을 형성하는 것, 절연막을 식각하여 광 도파로의 상부면을 노출시키는 오프닝을 형성하는 것, 노출된 광 도파로의 상부면으로부터 제2 단결정 반도체층을 형성하는 것, 제2 단결정 반도체층의 상부면으로부터 도펀트들로 도핑된 다결정 반도체층을 선택적으로 형성하는 것을 포함할 수 있다.
광 검출기, 광 도파로, 선택적 성장

公开(公告)号：KR1020120066438A

公开(公告)日：2012-06-22

申请号：KR1020100127787

申请日：2010-12-14

Applicant: 한국전자통신연구원

Inventor： 서동우 ,  김성복 ,  류호준

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/762

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to simplify a process by injecting impurities to a second nano wire to form a second source/drain area. CONSTITUTION: A substrate(100) includes a first top surface(T1), a second top surface, and a first vertical surface(P1). A first nano wire(110) is separated from the second top surface and is extended from the vertical surface. A second nano wire(112) includes a second impurity area. A gate electrode(116) is arranged on the first nano wire. A dielectric film(114) is interposed between the gate electrode and the first nano wire.

Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过将杂质注入到第二纳米线中以形成第二源极/漏极区域来简化工艺。 构成：衬底（100）包括第一顶表面（T1），第二顶表面和第一垂直表面（P1）。 第一纳米线（110）从第二顶表面分离并从垂直表面延伸。 第二纳米线（112）包括第二杂质区域。 栅电极（116）布置在第一纳米线上。 电介质膜（114）插入在栅电极和第一纳米线之间。

公开(公告)号：KR1020110062547A

公开(公告)日：2011-06-10

申请号：KR1020090119308

申请日：2009-12-03

Applicant: 한국전자통신연구원

Inventor： 김상훈 ,  김경옥 ,  김인규 ,  서동우 ,  주지호 ,  장기석

IPC: G02B6/12 ,  H01L31/02

CPC classification number: G02B6/12004 ,  G02B2006/12176 ,  G02B2006/12188 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

Abstract: PURPOSE: An optical detector and a manufacturing method thereof are provided to simplify the process of forming a polycrystalline semiconductor layer, by growing the polycrystalline semiconductor layer from a single-crystalline semiconductor layer selectively. CONSTITUTION: A first single-crystalline semiconductor layer(121) and an optical waveguide(123) are formed. The optical waveguide is projected from the first single-crystalline semiconductor layer. An insulation layer(130,140) is formed on the first single-crystalline semiconductor layer. The insulation layer covers the optical waveguide. An opening(131) is formed by etching the insulation layer. The opening reveals the top surface of the optical waveguide. A second single-crystalline semiconductor layer(132) is formed in the opening. A polycrystalline semiconductor layer(133) doped with dopants is selectively formed, from the top surface of the second single-crystalline semiconductor layer.

Abstract translation: 目的：通过选择性地从单晶半导体层生长多晶半导体层，提供光学检测器及其制造方法，以简化形成多晶半导体层的工艺。 构成：形成第一单晶半导体层（121）和光波导（123）。 光波导从第一单晶半导体层突出。 在第一单晶半导体层上形成绝缘层（130,140）。 绝缘层覆盖光波导。 通过蚀刻绝缘层形成开口（131）。 开口显示光波导的顶表面。 在开口中形成第二单晶半导体层（132）。 从第二单晶半导体层的顶表面选择性地形成掺杂有掺杂剂的多晶半导体层（133）。

公开(公告)号：KR1020100072609A

公开(公告)日：2010-07-01

申请号：KR1020080131060

申请日：2008-12-22

Applicant: 한국전자통신연구원

Inventor： 김인규 ,  권오균 ,  서동우 ,  김경옥

IPC: H01L21/31 ,  H01L21/324

CPC classification number: H01L21/2007 ,  H01L21/76251

Abstract: PURPOSE: A manufacturing method of a semiconductor device is provided to improve reliability through controlling thickness of an upper layer by forming an insulating layer without the loss of the thickness of an upper layer by using an inhibiting oxidation layer. CONSTITUTION: A first and second layers(110,130) are formed on the top of a substrate. An ion implantation layer(120) is formed between the first and second layers. An inhibiting oxidation layer(150) is formed on the second layer. By performing an annealing process, the loss of the second layer is controlled with the oxidation stop layer. An insulating layer is formed between the first and second layers. The oxidation stop layer comprises a poly-silicon or a crystalline silicon.

Abstract translation: 目的：提供半导体器件的制造方法，通过使用抑制氧化层，通过形成绝缘层而不损失上层的厚度来控制上层的厚度来提高可靠性。 构成：在衬底的顶部上形成第一和第二层（110,130）。 在第一和第二层之间形成离子注入层（120）。 在第二层上形成抑制氧化层（150）。 通过进行退火处理，用氧化停止层控制第二层的损失。 在第一和第二层之间形成绝缘层。 氧化停止层包括多晶硅或结晶硅。

公开(公告)号：KR1020100064592A

公开(公告)日：2010-06-15

申请号：KR1020080123097

申请日：2008-12-05

Applicant: 한국전자통신연구원

Inventor： 김인규 ,  서동우 ,  김경옥

IPC: H01S5/10 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/132

Abstract: PURPOSE: A methods of an optical waveguide is provided to form a core and cladding by oxidizing an active region which is defined through the trench of a semiconductor substrate. CONSTITUTION: An active region is defined by forming a trench in a semiconductor substrate(100). An active region is partly oxidized. A core includes a part of the active region which is not oxidized. An optical signal passes a through core. A cladding includes a part of the active region which is oxidized. A capping semiconductor pattern is formed on the top side and the upper of the active region in partial oxidation process of the active region. The lower side of the active region is exposed by the capping semiconductor pattern. The cladding is formed by oxidizing the lower part and capping semiconductor pattern of the active region.

Abstract translation: 目的：提供光波导的方法以通过氧化通过半导体衬底的沟槽限定的有源区来形成芯和包层。 构成：通过在半导体衬底（100）中形成沟槽来限定有源区。 活性区被部分氧化。 核心包括一部分未被氧化的活性区域。 光信号通过芯。 包层包括被氧化的有源区的一部分。 在有源区的部分氧化过程中，在有源区的顶侧和上部形成封装半导体图案。 有源区的下侧由封盖半导体图案露出。 通过氧化活性区域的下部和封盖半导体图案形成包层。

公开(公告)号：KR1020100063607A

公开(公告)日：2010-06-11

申请号：KR1020090025685

申请日：2009-03-26

Applicant: 한국전자통신연구원

Inventor： 김상훈 ,  김경옥 ,  서동우 ,  주지호

IPC: C30B25/02 ,  C30B29/08 ,  H01L21/205 ,  H01L31/10

Abstract: PURPOSE: A growth method of a germanium single crystal thin film having a negative photoconductive property and an optical detector using the same are provided to improve a penetration dislocation density and a surface roughness by forming the germanium single crystal thin film of a high grade on a silicon substrate. CONSTITUTION: A germanium thin film is grown up(S11) on the silicon substrate in a low temperature. The germanium thin film is grown up by increasing temperature(S12). The germanium thin film is grown up(S13) in the high temperature. Each growth step is processed using a low pressure chemical vapor deposition. The deposition rate at the increasing temperature germanium growth is similar to the deposition rate at the low temperature germanium growth.

Abstract translation: 目的：提供具有负光导性的锗单晶薄膜和使用其的光学检测器的生长方法，以通过在高温下形成高等级的锗单晶薄膜来提高穿透位错密度和表面粗糙度 硅衬底。 构成：在低温下在硅衬底上长大（S11）锗薄膜。 锗薄膜通过增加温度而长大（S12）。 锗薄膜在高温下长大（S13）。 使用低压化学气相沉积处理每个生长步骤。 在增加温度锗生长时的沉积速率与低温锗生长时的沉积速度相似。