公开(公告)号：KR100489802B1

公开(公告)日：2005-05-16

申请号：KR1020020081474

申请日：2002-12-18

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  양일석 ,  박일용 ,  유병곤 ,  김종대

IPC: H05B33/00

CPC classification number: H01L21/823462 ,  H01L27/088 ,  H01L27/1203

Abstract: 본 발명은 고전압 및 저전압 소자의 구조와 그 제조방법에 관한 것으로, SOI 기판 위에 형성된 고전압 및 저전압 소자의 구조에 있어서, SOI 기판 내의 실리콘 소자 영역의 높이가 고전압 소자 영역 보다 저전압 소자 영역이 높도록 단차가 있고, 고전압 소자가 형성되는 실리콘소자 영역의 두께는 저전압 소자의 소스 및 드레인의 불순물의 접합깊이와 일치되도록 형성하는 것을 특징으로 한다. 따라서, SOI 기판 내의 실리콘 소자영역을 고전압 소자 영역 및 저전압 소자 영역으로 나누어 산화막 성장법을 통해 단차를 두어 차별화 하므로, 낮은 접합 캐패시턴스를 갖는 고전압 소자를 제조할 수 있고, 기존의 CMOS 공정 및 소자 특성과 호환성을 갖는 저전압 소자를 동시에 제조할 수 있는 효과가 있다.

公开(公告)号：KR100452947B1

公开(公告)日：2004-10-14

申请号：KR1020020077598

申请日：2002-12-07

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  유병곤 ,  김종대

IPC: H01L27/12

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to be compatible with a process for fabricating an analog CMOS(complementary-metal-oxide-semiconductor) device of a sub micron class by forming sources and drains of high and low voltage devices in a well region formed in a silicon device region of a SOI(silicon-on-insulator) substrate. CONSTITUTION: The silicon device region(3) is patterned to respectively form a trench in an isolation region and a capacitor formation region between high and low voltage device regions. A drift region of the first conductivity type is formed in the silicon device region of the high voltage device region. Wells of the second and first conductivity types are formed in the drift region and the silicon device region of the high and low voltage device regions. An isolation layer(10) is formed in the trench. A field oxide layer(11) is formed in the silicon device region of the high voltage device region. Channel ions are implanted into the silicon device region of the high and low voltage device regions. Thick and thin gate oxide layers are formed in the high and low voltage device regions, respectively. A gate electrode(14a,14b) is formed on the channel region of the high and low voltage device regions while a lower electrode(14c) is formed in the capacitor formation region. Sources and drains(17a,17b) are formed in the wells of the high and low voltage device regions. An insulation layer(18) and an upper electrode(19) are sequentially formed on the lower electrode of the capacitor formation region.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以与用于制造亚微米级的模拟CMOS（互补金属氧化物半导体）器件的工艺兼容，所述方法通过将高压器件和低压器件的源极和漏极形成为 形成在SOI（绝缘体上硅）衬底的硅器件区中的阱区。 构成：硅器件区（3）被图案化以分别在高压器件区和低压器件区之间的隔离区和电容器形成区中形成沟槽。 第一导电类型的漂移区域形成在高压器件区域的硅器件区域中。 第二和第一导电类型的阱在高压和低压器件区的漂移区和硅器件区中形成。 隔离层（10）形成在沟槽中。 场氧化物层（11）形成在高压器件区的硅器件区中。 通道离子被注入高压和低压器件区域的硅器件区域。 厚和薄的栅氧化层分别在高压和低压器件区域中形成。 在高压和低压器件区的沟道区上形成栅电极（14a，14b），而在电容器形成区中形成下电极（14c）。 源极和漏极（17a，17b）形成在高压和低压器件区域的阱中。 在电容器形成区域的下电极上顺序形成绝缘层（18）和上电极（19）。

公开(公告)号：KR1020040054436A

公开(公告)日：2004-06-25

申请号：KR1020020081474

申请日：2002-12-18

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  양일석 ,  박일용 ,  유병곤 ,  김종대

IPC: H05B33/00

CPC classification number: H01L21/823462 ,  H01L27/088 ,  H01L27/1203

Abstract: PURPOSE: A structure of a high-voltage element, a structure of a low-voltage element, and a fabricating method thereof are provided to form the high-voltage element having low junction capacitance and the low-voltage element having a compatible characteristic by dividing a silicon element region into a high-voltage element region and a low-voltage element region. CONSTITUTION: A first oxide layer and a nitride layer are sequentially deposited on an SOI substrate including a bottom substrate(200), a buried oxide layer(202), and a top silicon layer. A high-voltage element region is defined on an entire structure and the nitride layer and the first oxide layer are removed from the high-voltage element region. A second oxide layer is grown on the high-voltage element region. The second oxide layer, the remaining nitride layer, and the first oxide layer are removed therefrom. An isolation region is defined. A high-voltage element region and a low voltage element region are formed on the isolation region by etching the top silicon region. A p-well(214) is formed on the low-voltage element region. A p-well(218) and a floating region(216) are formed on the high-voltage element region. A thin gate insulating layer(228) is formed on the low-voltage element region. A thick gate insulating layer(226) is formed on the high-voltage element region. A plurality of gate electrodes(230a,230b), a plurality of LDD regions(232a-232c), a plurality of sidewall oxide layers, and a plurality of source/drain regions(236a-236d) are formed on the low-voltage element region and the high-voltage element region. An interlayer dielectric(238) is deposited on a top part of the entire structure. A source electrode(240a) and a drain electrode(242a) are formed thereon.

Abstract translation: 目的：提供高电压元件的结构，低电压元件的结构及其制造方法，以形成具有低结电容的高电压元件，并且通过划分具有兼容特性的低电压元件 将硅元件区域变成高电压元件区域和低电压元件区域。 构成：第一氧化物层和氮化物层依次沉积在包括底部衬底（200），掩埋氧化物层（202）和顶部硅层的SOI衬底上。 在整个结构上限定高电压元件区域，并且从高电压元件区域去除氮化物层和第一氧化物层。 在高电压元件区域上生长第二氧化物层。 从其去除第二氧化物层，剩余氮化物层和第一氧化物层。 定义了隔离区域。 通过蚀刻顶部硅区域，在隔离区域上形成高电压元件区域和低电压元件区域。 在低电压元件区域上形成p阱（214）。 在高电压元件区域上形成p阱（218）和浮动区域（216）。 在低电压元件区域上形成薄栅极绝缘层（228）。 在高电压元件区域上形成厚栅极绝缘层（226）。 多个栅极（230a，230b），多个LDD区（232a-232c），多个侧壁氧化物层和多个源/漏区（236a-236d）形成在低电压元件 区域和高压元件区域。 层间电介质（238）沉积在整个结构的顶部。 在其上形成源电极（240a）和漏电极（242a）。

公开(公告)号：KR100385859B1

公开(公告)日：2003-06-02

申请号：KR1020000082805

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  노태문 ,  이대우 ,  조경익

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

Abstract: A method for manufacturing a trench-gate type power semiconductor device is provided A drift region having a low concentration of a first conductivity type and a body region of a second conductivity type are formed on a semiconductor substrate having a high concentration of the first conductivity type A trench is formed using a nitride layer pattern and a sidewall oxide layer formed at sidewalls of the nitride layer pattern as a mask, and then the sidewall oxide layer is removed The corners of the trench are rounded by performing a heat treatment in a hydrogen atmosphere A source region having a high concentration of the first conductivity type is formed using the nitride layer pattern as a mask. The nitride layer pattern is removed, and an upper oxide layer pattern is formed to cover a predetermined portion of the source region and the gate conductive layer. A body contact region of the second conductivity type is formed using the upper oxide layer pattern as a mask A source electrode is formed to be electrically connected to the body contact region, and a drain electrode is formed to be electrically connected to the semiconductor substrate

Abstract translation: 提供了一种用于制造沟槽栅极型功率半导体器件的方法。在具有第一导电类型的高浓度的半导体衬底上形成具有低浓度的第一导电类型的漂移区和第二导电类型的体区 使用形成在氮化物层图案的侧壁处的氮化物层图案和侧壁氧化物层作为掩模来形成沟槽，然后去除侧壁氧化物层。通过在氢气氛中进行热处理使沟槽的拐角变圆 使用氮化物层图案作为掩模形成具有第一导电类型的高浓度的源极区域。 去除氮化物层图案，并且形成上氧化物层图案以覆盖源区和栅导电层的预定部分。 使用上氧化层图案作为掩模形成第二导电类型的体接触区域。源电极形成为电连接到体接触区域，并且漏电极形成为电连接到半导体衬底

公开(公告)号：KR1020030034584A

公开(公告)日：2003-05-09

申请号：KR1020010066228

申请日：2001-10-26

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  구진근 ,  이대우 ,  김상기 ,  김종대 ,  노태문 ,  박일용

IPC: H02M3/28

Abstract: PURPOSE: A multi-output DC-DC converter is provided to be capable of outputting a multi-level voltage using one embedded inductor having a plurality of output taps. CONSTITUTION: An inductor part(300) is supplied with an input voltage and has a plurality of output taps which are spaced apart from each other. The first switching unit(230) consists of a plurality of transistors cascaded between each output tap of the inductor part and a common node and controlled by corresponding control signals. The second switching unit(210) is connected between the common node and the output terminal and is controlled by the control signal. The third switching unit(220) consists of a plurality of transistors which are connected in parallel between the common node and a ground voltage and are selectively operated according to corresponding control signals.

Abstract translation: 目的：提供多输出DC-DC转换器，以便能够使用具有多个输出抽头的一个嵌入式电感器输出多电平电压。 构成：电感器部件（300）被提供有输入电压并且具有彼此间隔开的多个输出抽头。 第一开关单元（230）由在电感器部分的每个输出抽头和公共节点之间级联并由相应的控制信号控制的多个晶体管组成。 第二开关单元（210）连接在公共节点和输出端子之间，并由控制信号控制。 第三开关单元（220）由在公共节点和接地电压之间并联连接的多个晶体管组成，并根据相应的控制信号选择性地工作。

公开(公告)号：KR100345305B1

公开(公告)日：2002-07-25

申请号：KR1020000082311

申请日：2000-12-26

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  김종대 ,  조경익

IPC: H01L21/334

公开(公告)号：KR100341214B1

公开(公告)日：2002-06-20

申请号：KR1019990059752

申请日：1999-12-21

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  이대우 ,  남기수 ,  김종대 ,  김상기 ,  구진근

IPC: H01L27/088

Abstract: 본발명은트렌치게이트로폴리실리콘과금속을적층하여형성하므로써고속동작이가능하도록한 전력 UMOSFET의제조방법에관한것으로서, 전력 UMOSFET 제조방법에있어서, 고농도제1도전형의실리콘기판에저농도제1도전형의실리콘에피층을성장시키는단계; 상기에피층상에얇은산화막을성장시킨후 몸체를형성하기위한제2도전형불순물을이온주입하고열처리하는단계; 상기산화막위에우물영역이오픈된질화막패턴을형성하고고농도제2도전형불순물을이온주입하고노출된부분의상기산화막을성장시키면서고온열처리하여우물을형성하는단계; 고농도의제1도전형불순물을이온주입하여소스접합을형성하는단계; 상기산화막을제거하고절연막을형성한후 게이트영역의상기절연막, 소스접합, 몸체및 에피층의일부를건식식각하여트렌치를형성하는단계; 상기트렌치내부에게이트산화막을형성한후, 게이트물질로서도핑된다결정실리콘과금속을적층하는단계; 상기다결정실리콘과금속의일부를식각한후, 그위에층간절연막을증착하는단계; 및상기층간절연막을선택적으로식각하여상기소스접합과상기금속에각기콘택되는전극을형성하고, 상기실리콘기판하단에드레인을형성하는단계를포함하여이루어짐을특징으로한다.

公开(公告)号：KR100341213B1

公开(公告)日：2002-06-20

申请号：KR1019990061152

申请日：1999-12-23

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  조경익

IPC: H01L27/092

Abstract: 본발명은반도체기술에관한것으로, 특히고전압전력소자에관한것이며, 더자세히는원형(race-track type) 전류제어 LDMOS(lateral double diffused MOS) 전력소자에관한것이다. 본발명은드레인부근에서의전류집중효과를완화시켜소자의전압이득을높이며, 고전계영역에서핫캐리어(hot career)에대한소자신뢰성을개선하고, 항복전압을높일수 있고, 전류제어가용이한원형전류제어전력소자를제공하는데그 목적이있다. 본발명의트렌치드레인구조를갖는원형전류제어전력소자는채널영역이표류영역에서부분적으로돌출된톱니구조를가지며, 동시에드레인은채널과채널사이로돌출된톱니형트렌치구조를가진다. 즉, 본발명에서제안하는원형전류제어전력소자는원형의 LDMOS 소자로서톱니형채널사이에는필드산화막이있어서채널과채널간을격리시키며, 이에대응하여톱니형트렌치드레인이표류영역의길이만큼떨어져서톱니형채널과서로어긋나게맞물려있다. 따라서, 톱니형채널과톱니형트렌치드레인의폭 및트렌치깊이를조절함으로써드레인전류를쉽게제어할수 있으며, 드레인을톱니형트렌치구조로형성함으로써캐리어가수평및 수직방향으로분산되어결과적으로전류집중효과를완화시킴으로서종래의원형전력소자보다소자의출력저항을증가시켜전압이득을증가시킬뿐만아니라, 온(On) 상태에서의항복전압을높이며, 핫캐리어에의한소자열화특성을개선시킬수 있다. 그리고 p형에피층, p웰층및 n형표류영역등에대한불순물농도분포, 채널및 드레인의선폭길이등을최적화하고, RESURF(REduced SURface Field) 특성을이용하여소자의성능을더욱개선시킬수 있다.

公开(公告)号：KR100298194B1

公开(公告)日：2001-11-02

申请号：KR1019990041794

申请日：1999-09-29

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  조경익

IPC: H01L21/22

Abstract: 본발명은채널영역에트렌치를형성하여짧은채널효과를방지하며동시에표류층에서게이트가장자리에트렌치를형성하여공핍층의확장을다소억제시킴으로써결과적으로소자의 RESURF 특성이촉진되어항복전압및 온(on) 저항특성을개선시킬수 있는트렌치게이트구조의전력소자에관한것이다. 본발명의실시예에따른전력소자는제1 도전형의실리콘기판상에제1 도전형의매몰층과제2 도전형의에피층이형성되며, 제1 도전형의매몰층위에는채널영역을이루는제1 도전형의확산층이형성되고, 제2 도전형의에피층은그 상부에형성된제2 도전형의표류층을둘러싸며, 제1 도전형의확산층표면에는소오스영역및 제1 트렌치가형성되고, 상기제2 도전형의표류층표면에는제2 트렌치및 드레인영역이형성된다. 제1 트렌치는게이트전극으로채워지며, 제2 트렌치는일부또는전부가게이트전극으로덮인다. 그리고, 이중 RESURF 효과를얻기위하여제2 도전형표류층에는제2 트렌치주변을감싸는제1 도전형의얕은불순물층이형성된다.

公开(公告)号：KR100289049B1

公开(公告)日：2001-10-24

申请号：KR1019970069537

申请日：1997-12-17

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  김종대 ,  김상기 ,  구진근 ,  남기수

IPC: H01L29/78

Abstract: PURPOSE: A power device having a double field plate structure is provided to improve a breakdown voltage and an on-resistance of a device by controlling a width of a depletion layer using a voltage difference applied from a drain voltage to a gate and a source electrode of a LDMOS(Lateral Double Diffused MOS). CONSTITUTION: An n-type drift region(4) and a p-type diffused layer(5) are formed on a p-type epitaxial layer(4). A drain region(8a) is formed on the n-type drift region(4) and a source region(8) is formed on the p-type diffused layer(5). A field insulating layer(3) is formed on a center portion of the drift region(4). A gate electrode(7) intervening a gate insulating layer(6) onto the p-type diffused layer(5) and a source/drain electrode(11,12) are formed, thereby forming a power device. The gate electrode having a gate field plate structure is extended in a longitude direction from the gate region to a portion of the field insulating layer according to a top surface of the drift region. The source electrode having a source field plate is extended from the source region to a portion of an interlayer dielectric of the drift region.