公开(公告)号：AU651747B2

公开(公告)日：1994-07-28

申请号：AU2979492

申请日：1992-12-02

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/28 ,  G06F13/22 ,  G06F13/36 ,  G06F13/362 ,  G06F13/20

Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.

公开(公告)号：CA2080210A1

公开(公告)日：1993-07-03

申请号：CA2080210

申请日：1992-10-08

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：BR9203811A

公开(公告)日：1993-04-27

申请号：BR9203811

申请日：1992-09-30

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/30 ,  G06F13/362 ,  G06F13/00

Abstract: An arbiter with an arbitration hold feature is discloses which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.

公开(公告)号：CA2071376A1

公开(公告)日：1993-04-16

申请号：CA2071376

申请日：1992-06-16

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/30 ,  G06F13/362 ,  G06F13/12 ,  G06F13/18

Abstract: BC9-91-082 CONTROLLING BUS ALLOCATION USING ARBITRATION HOLD An arbiter with an arbitration hold feature is discloses which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.

公开(公告)号：CA2071347A1

公开(公告)日：1993-04-16

申请号：CA2071347

申请日：1992-06-16

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  LOHMAN TERENCE J

IPC: G06F12/00 ,  G06F5/06 ,  G11C7/00 ,  G06F13/16

Abstract: BC9-91-072 EXPANDABLE HIGH PERFORMANCE FIFO DESIGN An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.