公开(公告)号：BR112019007567B1

公开(公告)日：2022-07-05

申请号：BR112019007567

申请日：2017-10-02

Applicant: IBM

Inventor： DAN GREINER ,  TIMOTHY SLEGEL ,  CHRISTIAN ZOELLIN ,  VOLODYMYR PAPROTSKI ,  TAMAS VISEGRADY ,  REINHARD THEODOR BUENDGEN ,  JANATHAN BRADBURY ,  ADITYA NITIN PURANIK ,  CHRISTIAN JACOBI

IPC: H04L9/06 ,  H04L9/32

Abstract: Uma instrução para executar cifragem e autenticação é executada. A execução inclui a cifragem de um conjunto de dados fornecidos pela instrução para obter dados cifrados e colocar os dados cifrados em um local designado. Ela inclui ainda a autenticação de um conjunto de dados adicional fornecido pela instrução, em que a autenticação gera pelo menos uma parte de uma etiqueta de autenticação de mensagens. Pelo menos uma parte da etiqueta de autenticação de mensagens é armazenada em um local.

公开(公告)号：IL284334D0

公开(公告)日：2021-08-31

申请号：IL28433421

申请日：2021-06-23

Applicant: IBM ,  CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/451 ,  G06F9/54 ,  G06F11/07

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

公开(公告)号：BR112021008844A2

公开(公告)日：2021-08-17

申请号：BR112021008844

申请日：2019-11-05

Applicant: IBM

Inventor： ADITYA NITIN PURANIK ,  BRUCE CONRAD GIAMEI ,  CHRISTIAN GERHARD ZOELLIN ,  CHRISTIAN JACOBI ,  DONALD WILLIAM SCHMIDT ,  JONATHAN BRADBURY ,  MARK FARRELL ,  MARTIN RECKTENWALD ,  TIMOTHY SLEGEL

IPC: G06F9/30

Abstract: instrução de separação e fusão para um processador de propósito geral. uma instrução de separar listas é provida para executar uma operação de separação e/ou uma fusão. a instrução é uma instrução de máquina de arquitetura de uma arquitetura de conjunto de instruções e é executada por um processador de propósito geral do ambiente de computação. a execução inclui separar uma pluralidade de listas de entrada para obter uma ou mais listas de saída separadas, que são transmitidas.

公开(公告)号：BR112014031432B1

公开(公告)日：2021-07-27

申请号：BR112014031432

申请日：2012-11-22

Applicant: IBM

Inventor： CHRISTIAN JACOBI ,  DAN GREINER ,  TIMOTHY SLEGEL

IPC: G06F9/46

Abstract: instrução de armazenamento não transacional. uma instrução de armazenamento não transacional, executada em modo de execuçao transacional, realiza armazenamentos que estão retidos, mesmo se uma operação associada a instrução aborta. os armazenamentos incluem informações especificadas pelo usuário que podem facilitar a depuração de uma transação abortada.

公开(公告)号：IL281734D0

公开(公告)日：2021-05-31

申请号：IL28173421

申请日：2021-03-22

Applicant: IBM ,  BRUCE CONRAD GIAMEI ,  MARTIN RECKTENWALD ,  DONALD W SCHMIDT ,  TIMOTHY SLEGEL ,  ADITYA N PURANIK ,  MARK S FARRELL ,  CHRISTIAN JACOBI ,  JONATHAN D BRADBURY ,  CHRISTIAN ZOELLIN

Inventor： BRUCE CONRAD GIAMEI ,  MARTIN RECKTENWALD ,  DONALD W SCHMIDT ,  TIMOTHY SLEGEL ,  ADITYA N PURANIK ,  MARK S FARRELL ,  CHRISTIAN JACOBI ,  JONATHAN D BRADBURY ,  CHRISTIAN ZOELLIN

IPC: G06F9/30 ,  G06F9/38

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：GB2578070B

公开(公告)日：2020-09-09

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2577468B

公开(公告)日：2020-08-05

申请号：GB202000448

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  CHRISTIAN JACOBI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS

IPC: G06F12/0875 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1027

Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

公开(公告)号：GB2578070A

公开(公告)日：2020-04-15

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：MX371225B

公开(公告)日：2020-01-09

申请号：MX2019003604

申请日：2017-10-02

Applicant: IBM

Inventor： TIMOTHY SLEGEL ,  CHRISTIAN JACOBI ,  JONATHAN BRADBURY ,  DAN GREINER ,  CHRISTIAN ZOELLIN ,  VOLODYMYR PAPROTSKI ,  TAMAS VISEGRADY ,  REINHARD THEODOR BUENDGEN ,  ADITYA NITIN PURANIK

IPC: H04L9/06 ,  H04L9/32

Abstract: Se ejecuta una instrucción para llevar a cabo el cifrado y autenticación. La ejecución incluye cifrar un conjunto de datos proporcionados por la instrucción para obtener datos cifrados y colocar los datos cifrados en una ubicación designada. Además incluye autenticar un conjunto de datos adicional proporcionado por la instrucción, en el cual la autenticación genera al menos una parte de una etiqueta de autenticación de mensaje. Dicha al menos una parte de la etiqueta de autenticación de mensaje se almacena en una ubicación seleccionada.

公开(公告)号：MX2019003604A

公开(公告)日：2019-06-17

申请号：MX2019003604

申请日：2017-10-02

Applicant: IBM

Inventor： TIMOTHY SLEGEL ,  CHRISTIAN JACOBI ,  JONATHAN BRADBURY ,  DAN GREINER ,  CHRISTIAN ZOELLIN ,  VOLODYMYR PAPROTSKI ,  TAMAS VISEGRADY ,  REINHARD THEODOR BUENDGEN ,  ADITYA NITIN PURANIK

IPC: H04L9/06 ,  H04L9/32

Abstract: Se ejecuta una instrucción para llevar a cabo el cifrado y autenticación. La ejecución incluye cifrar un conjunto de datos proporcionados por la instrucción para obtener datos cifrados y colocar los datos cifrados en una ubicación designada. Además incluye autenticar un conjunto de datos adicional proporcionado por la instrucción, en el cual la autenticación genera al menos una parte de una etiqueta de autenticación de mensaje. Dicha al menos una parte de la etiqueta de autenticación de mensaje se almacena en una ubicación seleccionada.