公开(公告)号：DE10324491B4

公开(公告)日：2005-07-14

申请号：DE10324491

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MALIK RAIEEV ,  RENGARAJAN RAIESH

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.

公开(公告)号：DE10344862A1

公开(公告)日：2004-04-15

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE10310571A1

公开(公告)日：2003-10-02

申请号：DE10310571

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  MCSTAV KEVIN

IPC: H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/108

Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.