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    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS
    1.
    发明申请
    DUAL GATE OXIDE PROCESS FOR UNIFORM OXIDE THICKNESS 审中-公开
    用于均匀氧化物厚度的双栅氧化工艺

    公开(公告)号：WO0237561A2

    公开(公告)日：2002-05-10

    申请号：PCT/US0143859

    申请日：2001-11-06

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

    CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

    Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

    Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

    Method for producing electroconductive film in semiconductor process
    2.
    发明专利
    Method for producing electroconductive film in semiconductor process 审中-公开
    在半导体工艺中生产电极膜的方法

    公开(公告)号：JP2006214002A

    公开(公告)日：2006-08-17

    申请号：JP2005355599

    申请日：2005-12-09

    Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

    Inventor： HINTZE BERND ,  KUDELKA STEPHAN ,  SUNDQVIST JONAS

    IPC: C23C16/34 ,  H01B13/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/822 ,  H01L27/04

    CPC classification number: H01L21/3141 ,  H01L21/318 ,  H01L21/76846 ,  H01L28/60

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor process for forming an electroconductive film having small surface roughness and no continuous particle boundary.
    SOLUTION: The electroconductive film 11 comprises two or more different metal nitrides 21, 22 and 23, which are deposited on a substrate 10. Thereby, the electroconductive film 11 acquires a structure consisting of particles with smaller sizes than those in an electroconductive film produced from only titanium nitride. The electroconductive film 11 also acquires a smoother surface and smaller thickness than those of a film made of pure titanium nitride.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种半导体工艺，用于形成具有小的表面粗糙度和没有连续的粒子边界的导电膜。 解决方案：导电膜11包含沉积在基板10上的两种或更多种不同的金属氮化物21,22和23.由此，导电膜11获得由尺寸小于导电膜 仅由氮化钛制成的薄膜。 导电膜11还具有比由纯氮化钛制成的膜更平滑的表面和更小的厚度。 版权所有（C）2006，JPO＆NCIPI

    4.
    发明专利
    未知

    公开(公告)号：DE10344862A1

    公开(公告)日：2004-04-15

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    7.
    发明专利
    未知

    公开(公告)号：DE10296608T5

    公开(公告)日：2004-04-22

    申请号：DE10296608

    申请日：2002-04-08

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DYER THOMAS W ,  KUDELKA STEPHAN ,  PRAKASH V C JAI ,  RADENS CARL

    IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

    Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

    9.
    发明专利
    未知

    公开(公告)号：DE10344862B4

    公开(公告)日：2007-12-20

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

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