公开(公告)号：GB2503176A

公开(公告)日：2013-12-18

申请号：GB201317939

申请日：2012-01-16

Applicant: IBM

Inventor： KHAKIFIROOZ ALI ,  CHENG KANGGUO ,  DORIS BRUCE ,  HAENSCH WILFRIED E A ,  HARAN BALASUBRAMANIAN ,  KULKARNI PRANITA

IPC: H01L21/8244 ,  H01L21/768 ,  H01L21/8234

Abstract: A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

公开(公告)号：GB2486839A

公开(公告)日：2012-06-27

申请号：GB201204634

申请日：2010-09-08

Applicant: IBM

Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE ,  SHAHIDI GHAVAM G

IPC: H01L29/78 ,  H01L21/336

Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack (18), e.g., FET, located on an upper surface (14) of a semiconductor substrate (12). The structure further includes a first epitaxy semiconductor material (34) that induces a strain upon a channel (40) of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions (28) in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region (38) is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material (36) located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

公开(公告)号：AT427563T

公开(公告)日：2009-04-15

申请号：AT06777968

申请日：2006-07-25

Applicant: IBM

Inventor： DORIS BRUCE ,  COSTRINI GREGORY ,  GLUSCHENKOV OLEG ,  LEONG MEIKEI ,  SEONG NAKGEUON

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.