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公开(公告)号：DE3852185T2
公开(公告)日：1995-05-24
申请号：DE3852185
申请日：1988-01-26
Applicant: IBM
Inventor： GUPTA SATISH , LUMELSKY LEON , SEGRE MARC
Abstract: A frame buffer is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. :p. The writing of individual pixels in this array is enabled by energising the write enable pins to each memory chip directly. The data wires in the memory organisation are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same. :p.The frame buffer includes a selectively energisable plane mask for disabling desired planes of accessed pixels. By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one.
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公开(公告)号：DE3852045D1
公开(公告)日：1994-12-15
申请号：DE3852045
申请日：1988-01-26
Applicant: IBM
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公开(公告)号：DE3889136D1
公开(公告)日：1994-05-26
申请号：DE3889136
申请日：1988-01-26
Applicant: IBM
Inventor： GUPTA SATISH , LUMELSKY LEON , MANSFIELD ROBERT LOCKWOOD , ROMERO HECTOR GERARDO , SEGRE MARC , SPENCER ALEXANDER KOOS , ST CLAIR JOE CHRISTOPHER , WAGONER JAMES DONALD
Abstract: As the speed and capacity of graphics workstations and personal computers including graphics adapters increases, a display adapter which can be used either in such a high capacity stand alone graphics workstation or in conjunction with a large main frame host computer includes a first processor for managing adapter resources and controlling coordinate transformations; a system storage for storing instructions and data representing information to be displayed; a first-in, first-out input buffer for allowing asynchronous and overlapped communication between the graphics system and a host computer;a second processor for drawing vectors and manipulating areas to be displayed on the monitor;a frame buffer connected to the second processor for storing a bit map of data to be displayed; a colour palette connected to outputs of the frame buffer for providing appropriate colour signals to the monitor; and a hardware cursor circuit for controlling display of a cursor on the monitor.
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公开(公告)号：CA2067418A1
公开(公告)日：1993-01-23
申请号：CA2067418
申请日：1992-04-28
Applicant: IBM
Inventor： CHOI SUNG M , LUMELSKY LEON , PEEVERS ALAN W , PITTAS JOHN L
Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules (34). The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.
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Patent Agency Ranking46.发明专利
公开(公告)号：CA2043177A1
公开(公告)日：1991-12-21
申请号：CA2043177
申请日：1991-05-24
Applicant: IBM
Inventor： LUMELSKY LEON
IPC: G06F3/153 , G09G5/00 , G09G5/36 , G09G5/39 , G09G5/391 , G09G5/393 , G09G5/395 , G09G5/397 , G09G5/399 , H04N5/262 , H04N5/44
Abstract: Image conversion method and apparatus that provides for (a) storing in a first memory a first image field; (b) storing in a second memory a second image field; (c) reading the first and the second memories; (d) simultaneously displaying on a display screen the first and the second image fields as a single image frame; and (e) while performing the step of reading the method includes a step of storing in a third memory a third image field. The first, second and third memories are provided as a frame buffer having a 3x3 memory block organization. For image fields numbered 1, 2, 3, 4, 5...n.. the system of the invention reads the image fields two at a time in accordance with a predetermined sequence given by: 1 and 2, 2 and 3, 3 and 4, 4 and 5, ... (n - 1) and n, n and (n + 1). A high resolution frame length is selected to be longer than or shorter than a television field period. The phase difference between the two is measured and circuitry alters the predetermined read-out sequence to ensure that a field memory to be read will not also be required for simultaneously storing a next television field.
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公开(公告)号：CA1244958A
公开(公告)日：1988-11-15
申请号：CA502805
申请日：1986-02-26
Applicant: IBM
Inventor： LUMELSKY LEON
Abstract: PIXEL SLICE PROCESSOR A pixel processor includes a plurality of pixel slice processors and the architecture is arranged so that the pixel length is extendible by merely increasing the number of pixel slice processors. Each of the pixel slice processors is firstly interconnected with other pixel slice processors, and includes a plurality of registers, gates and multiplexers for selectively presenting to a processing means data derived from a variety of sources, including a frame buffer. The output of the processing means can be stored back in the frame buffer or directed to one or more registers in the associated pixel slice processor or/and to registers in other pixel slice processors. SIMD operation is accomplished for pixel lengths which are equal to or larger than the bit capacity of the pixel slice processors. In a particular embodiment of the invention, SIMD operation is effected on pixel lengths larger than the bit capacity of the pixel slice processors. For operating on k pixels simultaneously, the pixel slice processors are grouped into n/i groups of k processors each, where i indicates the bit handling capacity for each pixel slice processor and n is the pixel length. The architecture includes a data path to handle:
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公开(公告)号：BR8800248A
公开(公告)日：1988-09-13
申请号：BR8800248
申请日：1988-01-25
Applicant: IBM
Inventor： GUPTA SATISH , LUMELSKY LEON , MASFIELD ROBERT L , ROMERO HECTOR G JR , SEGRE MARC , SPENCER ALEXANDER K , CLAIR JOE C ST , WAGONER JAMES DONALD
Abstract: As the speed and capacity of graphics workstations and personal computers including graphics adapters increases, a display adapter which can be used either in such a high capacity stand alone graphics workstation or in conjunction with a large main frame host computer includes a first processor for managing adapter resources and controlling coordinate transformations; a system storage for storing instructions and data representing information to be displayed; a first-in, first-out input buffer for allowing asynchronous and overlapped communication between the graphics system and a host computer;a second processor for drawing vectors and manipulating areas to be displayed on the monitor;a frame buffer connected to the second processor for storing a bit map of data to be displayed; a colour palette connected to outputs of the frame buffer for providing appropriate colour signals to the monitor; and a hardware cursor circuit for controlling display of a cursor on the monitor.
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公开(公告)号：GB2336974B
公开(公告)日：2003-03-05
申请号：GB9908965
申请日：1999-04-21
Applicant: IBM
Inventor： LUMELSKY LEON
Abstract: A singlecast interactive radio system of the invention delivers digitized audio-based content to subscribers, upon their request, economically and with human voice quality. The system includes personal radio station servers, and a plurality of user terminals, and exploits one of the existing wireless communication networks as a transmission medium. A highly compressed voice-based information content is stored on data network servers, such as Internet World Wide Web servers. The personal radio station server stores multiple subscriber's profiles with topics of individual interest, assembles a content material from various Web sites according to the topics, and transmits the content to a subscriber's user terminal on subscriber's request over the wireless digital network. The user terminal restores voice-based material with at least AM-radio voice quality and transmission costs of such a material is very low in comparison to existing methods of voice communication, at least as a result of chosen compression algorithms. The user terminal optionally integrates, electrically and mechanically, a conventional radio and with a cellular phone equipment. The user can control system functions hands-free by issuing voice commands only. Such functions include, but are not limited to, cellular telephony voice dialing and control, secure network log-on based on voice identification, hands-free tuning to conventional radio-stations, changing audio playback level, and switching between functions. The user terminal also retrieves text material from the Internet or other data depositories, plays the material back as a computer-generated speech, digitizes a voice response from the user, and delivers the response to other e-mail addresses over related networks, including wired networks.
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公开(公告)号：DE69222247T2
公开(公告)日：1998-03-26
申请号：DE69222247
申请日：1992-07-16
Applicant: IBM
Inventor： CHOI SUNG MIN , LUMELSKY LEON , PEEVERS ALAN WESLEY , PITTAS JOHN LOUIS , SWART CALVIN BRUCE
Abstract: An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.
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