-
公开(公告)号：DE10102000B4
公开(公告)日：2004-04-08
申请号：DE10102000
申请日：2001-01-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN , SCHNEIDER HELMUT
IPC: H01L23/50 , H01L23/544 , H01L23/58
Abstract: A description is given of an integrated circuit having components and a method for checking a connection configuration of bonding pads. The integrated circuit has an identification circuit that identifies a connection of the bonding pads to external circuits. After the identification of the connected bonding pads, the data width of the input/output circuit is preferably programmed accordingly. In this way, self-detection and automatic programming are possible without data inputting from the outside.
-
公开(公告)号：DE10241982A1
公开(公告)日：2004-04-01
申请号：DE10241982
申请日：2002-09-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN
Abstract: Based on the desired delay, the output signal of a given signal delay element (103a,103b,103c) of a number of series-connected delay elements is used to produce the required delayed output (OUT). Each signal delay element comprises only a single inverter. The output signal may or may not be inverted w.r.t. the input signal (IN). Preferably, at least three delay elements are used. Switching device (116a,116b,135,136,137,138) are connected to the delay elements to activate them to provide the required delay.
-
公开(公告)号：DE10211912B4
公开(公告)日：2004-02-05
申请号：DE10211912
申请日：2002-03-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN
Abstract: The device is externally supplied with a supply voltage and has at least one useful circuit and a current supply for the useful circuit(s) with several current supply units. The current supply has a control unit (18) for comparing the supply voltage with a predefined demand value and for switching one or more switchable current supply units on or off depending on the comparison result. AN Independent claim is also included for the following: a method of controling a current supply for an integrated circuit.
-
公开(公告)号：DE10214304A1
公开(公告)日：2003-10-23
申请号：DE10214304
申请日：2002-03-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN , MINZONI ALESSANDRO
Abstract: Device for production of two signals (11,12) with a predetermined distance between corresponding signal flanks. Said device comprises: a first controllable time delay device (5A) for generation of a delayed internal clock signal from a first clock signal (3); a second controllable time delay device (5B) for generation of a displaced inverted clock signal from a complementary clock signal (4); and first and second control signal generators (6-8; 9-10). The invention also relates to a corresponding method.
-
公开(公告)号：DE10157865A1
公开(公告)日：2003-06-26
申请号：DE10157865
申请日：2001-11-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN , KLEHN BERND , SCHNABEL JOACHIM
Abstract: A programmable voltage pump (1) has a trim input (TRIM) for adjusting a desired output voltage (VNEG) as well as an output (OUT) where the output voltage is emitted. At the output (OUT) of the voltage pump there is a particularly easy means for generating an overflow level at the output of the voltage pump i.e. there is a switch (2) at the output that gives the option of earthing the output.
-
Patent Agency Ranking
公开(公告)号：DE10055001A1
公开(公告)日：2002-05-16
申请号：DE10055001
申请日：2000-11-07
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN , KAISER ROBERT , PFEFFERL PETER , DOMINIQUE SAVIGNAC , SCHNEIDER HELMUT
IPC: G11C11/401 , G11C5/02 , H01L21/8242 , H01L23/485 , H01L23/50 , H01L27/108 , H01L27/10
Abstract: The arrangement has cell fields (2-9) bounding on a central connector field (1), whereby a cell field has a matrix memory with row and column decoders (10,11) connected to address lines (12,13) and the connector field has connection pads electrically connected to the cell fields. A cell field is arranged at each of the four side edges of the connector field. The cell fields are arranged in a closed rim around the connector field.
-
公开(公告)号：DE102006024016B4
公开(公告)日：2008-04-03
申请号：DE102006024016
申请日：2006-05-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SPIRKL WOLFGANG , BROX MARTIN
IPC: G11C29/12
-
公开(公告)号：DE102006023173A1
公开(公告)日：2007-11-22
申请号：DE102006023173
申请日：2006-05-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN
IPC: G11C11/4072
Abstract: A memory device can be operated in a first operating state and a second operating state, where read access to memory cells can be performed in the first operating state. The memory device includes an activatable clock generator circuit to generate a clock signal. The clock generator circuit can be operated in an activated state, in which it generates the clock signal, and in a deactivated state, in which generation of the clock signal is suppressed. The activatable clock generator circuit is operated in the activated state at a time period after changeover of the memory device from the first operating state to the second operating state, and is changed over from the activated state to the deactivated state no later than after the period has elapsed.
-
公开(公告)号：DE102004004775B4
公开(公告)日：2006-11-23
申请号：DE102004004775
申请日：2004-01-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN
-
公开(公告)号：DE69830972D1
公开(公告)日：2005-09-01
申请号：DE69830972
申请日：1998-10-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BROX MARTIN
IPC: G11C11/41 , G11C7/18 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
Abstract: The chip has an array of memory cells arranged in rows and columns and each memory cell comprising a pair of bit lines for each column of memory cell. A capacitor (CINT) is provided between paired bit lines and an external capacitor (CEXT) is provided between adjacent bit line pairs. The spacing between paired bit lines is adjusted to be more than spacing between bit lines of each pair.
-
-
-
-
-
-
-
-
-
Search Results
56
records
(took 0.023 seconds)
