公开(公告)号：DE10124752B4

公开(公告)日：2006-01-12

申请号：DE10124752

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  CHRYSOSTOMIDES ATHANASIA

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/18

Abstract: The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

公开(公告)号：DE10124753A1

公开(公告)日：2002-12-12

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The method involves applying a binary memory cell signal(s) to a bit line pair(s), connecting the signal to a detection amplifier(s) depending on a cell field control signal(s), connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to a main data line pair(s) depending on a line control signal and outputting a binary output signal. The method involves applying at least one binary memory cell signal to at least one bit line pair (201t,201b), connecting the signal to at least one detection amplifier (202-0 to 202-7) depending on at least one cell field control signal, connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to at least one main data line pair depending on a line control signal and outputting a binary output signal

公开(公告)号：DE10145462B4

公开(公告)日：2006-01-26

申请号：DE10145462

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER

IPC: H03K17/0416 ,  H03K17/06 ,  H03K17/0814 ,  H03K17/10 ,  H03K17/687

公开(公告)号：DE10104701A1

公开(公告)日：2002-08-29

申请号：DE10104701

申请日：2001-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  PFEFFERL PETER ,  PFEIFFER JOHANN

IPC: G11C7/18 ,  G11C11/4096 ,  G11C7/14

Abstract: The method involves writing data into the memory simultaneously over the adjacent pairs of data lines. When reading data, data are only read from one of the pairs of data lines. Each data line is connected to a bit line via a switch and the switches to the four data lines are closed before writing data. Independent claims are also included for the following: a memory arrangement with at least two pairs of data lines.

公开(公告)号：DE10124753B4

公开(公告)日：2006-06-08

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.

公开(公告)号：DE10145462A1

公开(公告)日：2003-04-24

申请号：DE10145462

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER

IPC: H03K17/0416 ,  H03K17/0814 ,  H03K17/10 ,  H03K17/04 ,  H03K17/687

Abstract: An auxiliary transistor (D) is arranged in parallel with the field effect transistor (C), and is driven via an auxiliary control signal (d), in a way that reduces the degradation of the field effect transistor. A second field effect transistor (B) may be connected in series with the parallel arrangement of the first field effect transistor and the auxiliary transistor, and driven via a second control signal (b) in cascode connection. Independent claims are also included for a method for reducing the degradation of a field effect transistor, and for the use of the circuit for outputting a low level via the output driver stage.

公开(公告)号：DE10124752A1

公开(公告)日：2003-01-02

申请号：DE10124752

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  CHRYSOSTOMIDES ATHANASIA

IPC: G11C7/10 ,  G11C7/18 ,  G11C7/06

Abstract: A method for reading and storing memory cell array signals involving initially applying a binary memory cell array signal to at least one bit line pair and then switching the binary signal from the bit line pair (301) to a local data line pair (305) followed by switching the amplified binary signal to at least one main data line pair. Binary memory cell signals are then transferred from one location (100) to at least one first main data line pair (101,102) and binary memory cell signals are transferred from a second location (200) to a second main data line pair (201,202). The amplified, transferred binary signals are then outputted via the main data line pairs (101,102;201,202). An Independent claim is given for a reading and storing binary memory cell signals.

公开(公告)号：DE10055001A1

公开(公告)日：2002-05-16

申请号：DE10055001

申请日：2000-11-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KAISER ROBERT ,  PFEFFERL PETER ,  DOMINIQUE SAVIGNAC ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/50 ,  H01L27/108 ,  H01L27/10

Abstract: The arrangement has cell fields (2-9) bounding on a central connector field (1), whereby a cell field has a matrix memory with row and column decoders (10,11) connected to address lines (12,13) and the connector field has connection pads electrically connected to the cell fields. A cell field is arranged at each of the four side edges of the connector field. The cell fields are arranged in a closed rim around the connector field.