公开(公告)号：DE10115614A1

公开(公告)日：2002-10-10

申请号：DE10115614

申请日：2001-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C5/14 ,  G11C29/12 ,  H01L23/58 ,  G11C29/00 ,  H01L21/66 ,  H01L23/525

Abstract: The method involves supplying the device with a lower current from a standby current generator (11) in standby mode and from a normal current generator (12) in normal mode. The device is supplied by the standby generator in a test mode during a product development phase. The semiconducting component is supplied by the normal current generator in the production development phase alternatively or additionally to the standby current generator. AN Independent claim is also included for the following: a semiconducting memory component.

公开(公告)号：DE10026243C2

公开(公告)日：2002-04-18

申请号：DE10026243

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

IPC: G11C17/00 ,  G11C17/18 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/66 ,  H01L23/525 ,  G11C29/00

Abstract: The fuse state read-out method uses application of a voltage (Vblh) to the fuse which has a reduced voltage level relative to an internal voltage (Vint) of the semiconductor memory device, e.g. a voltage level which is reduced by between 20 and 30 % relative to an internal voltage of about 2 V, for defining the high potential of the bit lines (BL) of the memory cell field (6).

公开(公告)号：DE10063683A1

公开(公告)日：2002-03-14

申请号：DE10063683

申请日：2000-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

IPC: G11C17/18 ,  G11C29/00 ,  G11C14/00 ,  H01L23/525

Abstract: The circuit has a programmable connection that outputs an actual signal (E) depending on a current conducting state. A demand signal (D) can be taken from the output of a demand value memory (9) depending on a demand conducting state of the programmed connection and an evaluation circuit (26) receives the demand and actual signals and outputs an indicator signal (F) to indicate a deviation between the demand and actual measurement states.

公开(公告)号：DE10026737A1

公开(公告)日：2001-12-13

申请号：DE10026737

申请日：2000-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00 ,  H01L21/66 ,  H01L25/10

Abstract: The method involves applying a chip select signal to the data line or DQ line of one semiconductor module from several semiconductor modules (21-28). The address of incorrect memory cell is applied to all the modules at the same time, and the module corresponded to that address and being chosen by selection signal, is repaired.

公开(公告)号：FR2823901B1

公开(公告)日：2006-05-12

申请号：FR0204923

申请日：2002-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/40 ,  G11C29/44

Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

公开(公告)号：DE102004043050A1

公开(公告)日：2006-04-13

申请号：DE102004043050

申请日：2004-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPIRKL WOLFGANG ,  KILIAN VOLKER ,  KAISER ROBERT ,  BROX MARTIN

IPC: G01R31/3183 ,  G01R31/319 ,  G11C29/48

公开(公告)号：DE10136703C1

公开(公告)日：2003-04-17

申请号：DE10136703

申请日：2001-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAFFROTH THILO

IPC: G01R31/317 ,  G01R31/3187 ,  G11C29/00

Abstract: A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.

公开(公告)号：DE10113821C2

公开(公告)日：2003-02-06

申请号：DE10113821

申请日：2001-03-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEMMERT HEINRICH GEORG ,  KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G06F9/38 ,  G11C7/10 ,  G11C27/02 ,  G11C11/41

公开(公告)号：DE10119142A1

公开(公告)日：2002-10-31

申请号：DE10119142

申请日：2001-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00

Abstract: A method for detecting and repairing erroneous addresses in semiconductor modules, in which faulty addresses are recognized by a test procedure and temporarily stored in latches and then stored in electrical fuses by finally applying an increased lead voltage. The lead voltage is only applied when at the end of the test procedure, at least one faulty address is temporarily stored in the latches.

公开(公告)号：DE10117614A1

公开(公告)日：2002-10-17

申请号：DE10117614

申请日：2001-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A method for operating a semiconductor memory at a data transmission rate which is twice as fast. According to the invention, data read access and data write access is divided up into two memories. A first memory bank is operated at one speed which is offset by a factor of 0.5 in relation to the operating speed of the second memory bank and the data partial flows are combined at the output of the two memory banks to form a data flow at a frequency which is multiplied by two.