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公开(公告)号：DE60307834T2
公开(公告)日：2007-09-13
申请号：DE60307834
申请日：2003-08-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM
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公开(公告)号：SG129249A1
公开(公告)日：2007-02-26
申请号：SG200303515
申请日：2003-06-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： RUCKERBAUER HERMANN , KUZMENKA MAKSIM
Abstract: A connector (1) for the fixing and contact-making of a plurality of switching assemblies (2) having compatible interfaces on a substrate (3) has a plurality of receptacle devices (51,52,53,54) with contact elements (7) and also internal contact connections (10) between corresponding contact elements (7), as a result of which the length of connections between the switching assemblies (2) is reduced, signal propagation times are shortened and a higher clock rate for operation of the switching assemblies (2) is made possible.
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公开(公告)号：DE60308637D1
公开(公告)日：2006-11-09
申请号：DE60308637
申请日：2003-03-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM , CHENNUPATI SIVA RAGHURAM , BACHA ABDALLAH , MUFF SIMON
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公开(公告)号：DE60210170T2
公开(公告)日：2006-11-02
申请号：DE60210170
申请日：2002-07-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM , KOROTKOV KONSTANTIN
IPC: G06F13/40
Abstract: A memory system comprises a memory controller (14), a plurality of memory modules (10, 12) and a memory bus (16) connected to the memory controller (14) and branching into a plurality of sub-busses (20, 22), each of which is connected to a memory module (10, 12). A sub-bus (20, 22) has a diode (24, 26) associated therewith for isolating a memory module (10, 12) connected to that sub-bus (20, 22) from the memory bus (16).
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公开(公告)号：DE10330812B4
公开(公告)日：2006-07-06
申请号：DE10330812
申请日：2003-07-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： JAKOBS ANDREAS , RUCKERBAUER HERMANN , KUZMENKA MAKSIM
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Patent Agency Ranking
公开(公告)号：DE102004057231A1
公开(公告)日：2006-06-08
申请号：DE102004057231
申请日：2004-11-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： NYGREN AARON , KUZMENKA MAKSIM
IPC: G11C7/10 , G11C11/4093
Abstract: In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal which is to be transmitted, the signal to be transmitted is delayed between the two selected driver stages such that a given signal edge change appears at the output of the other of the selected driver stages at a different time from other signal edge which follow the one given signal edge change in time, at driver stages which are situated upstream of the other of the selected driver stages. The inventive output driver circuit accordingly has a delay element which can be used to influence the signal propagation time between the selected driver stages.
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公开(公告)号：DE102005036834A1
公开(公告)日：2006-03-16
申请号：DE102005036834
申请日：2005-08-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM
Abstract: A circuit board comprises a dielectric layer with a through-hole between a first and a second surface of the dielectric layer. An electrically conductive coating is arranged on a wall of the through-hole between the first and the second surface and a first signal trace is arranged on the first surface and a second signal trace is arranged on the second surface of the dielectric layer. The wire passing through the through-hole connects the first signal trace to the second signal trace.
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公开(公告)号：DE102004017863A1
公开(公告)日：2005-11-10
申请号：DE102004017863
申请日：2004-04-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BRAUN GEORG , KUZMENKA MAKSIM , RUCKERBAUER HERMANN
Abstract: A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
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公开(公告)号：DE10157874B4
公开(公告)日：2005-07-14
申请号：DE10157874
申请日：2001-11-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM
Abstract: A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a first memory unit. In addition, a second bus section is provided for supplying a second part of the control signals to a second memory unit. Finally, the device comprises redrive means for redriving the first part of the control signals from the first memory unit to the second memory unit and for redriving the second part of the control signals from the second memory unit to the first memory unit. A memory unit for such a device for supplying control signals comprises first inputs for receiving a first part of the control signals from a memory control, second inputs for receiving a second part of the control signals from at least one other memory unit, and outputs for redriving said first part of the control signals to said at least one other memory unit.
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公开(公告)号：DE60203605D1
公开(公告)日：2005-05-12
申请号：DE60203605
申请日：2002-06-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KUZMENKA MAKSIM
Abstract: A circuit part comprises a support (10, 12) and conductor teeth (14) provided on the support, wherein the conductor teeth (14) are designed to be electrically and mechanically connected to respective conductor teeth (14) provided on another support in the manner of a zipper. The teeth are provided with a spring mechanism to improve the electrical contact between adjacent teeth when connected. The spring mechanism comprises a respective gap formed in the teeth, wherein when connected, the teeth are compressed by reducing the gap so that a restoring force is produced.
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